From: lkcl Date: Thu, 16 Sep 2021 09:09:11 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~107 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2af1109513b89d95a337c6438e1583584a6c2761;p=libreriscv.git --- diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 4e5998ec2..141939691 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -28,7 +28,7 @@ Modes apply to Arithmetic and Logical SVP64 operations: *VL is altered as a result*. * **sat mode** or saturation: clamps each element result to a min/max rather than overflows / wraps. allows signed and unsigned clamping for both INT and FP. -* **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see [[appendix]] +* **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see [[svp64/appendix]] note that there are comprehensive caveats when using this mode. * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the *destination* predicate bit was zero. When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed. See appendix for details.