From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 8 Apr 2021 20:31:05 +0000 (+0100)
Subject: reduce jtag data bus width to 32, to match litex
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2af6d3f17c328d07719661106729f63c626e693a;p=libresoc-litex.git

reduce jtag data bus width to 32, to match litex
set (ignored) pc_i to 64 bit
remove mem_2.init cp
---

diff --git a/Makefile b/Makefile
index bd7734e..5ea2421 100644
--- a/Makefile
+++ b/Makefile
@@ -18,9 +18,6 @@ ls180:
 	cp build/ls180/gateware/ls180.v .
 	cp build/ls180/gateware/mem.init .
 	cp build/ls180/gateware/mem_1.init .
-	cp build/ls180/gateware/mem_2.init .
-	cp build/ls180/gateware/mem_3.init .
-	cp build/ls180/gateware/mem_4.init .
 	cp libresoc/libresoc.v .
 	yosys -p 'read_verilog libresoc.v' \
 	      -p 'read_verilog ls180.v' \
diff --git a/libresoc/core.py b/libresoc/core.py
index ebf214e..8fae419 100644
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -206,7 +206,7 @@ class LibreSoC(CPU):
         if "testgpio" in variant:
             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
         if jtag_en:
-            self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
+            self.jtag_wb = jtag_wb = wb.Interface(data_width=32, adr_width=30)
 
         self.srams = srams = []
         if "sram4k" in variant:
@@ -238,7 +238,7 @@ class LibreSoC(CPU):
             i_rst              = ResetSignal() | self.reset,
 
             # Monitoring / Debugging
-            i_pc_i             = 0,
+            i_pc_i             = Signal(64),
             i_pc_i_ok          = 0,
             i_core_bigendian_i = 0, # Signal(),
             o_busy_o           = Signal(),   # not connected