From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Jul 2020 21:32:56 +0000 (+0100)
Subject: add mtmsr tests (fail)
X-Git-Tag: div_pipeline~162^2~49
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b2ad4b0774f4a8cd583a7b7d323bba5e5fb6072;p=soc.git

add mtmsr tests (fail)
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index fbbbb75f..fa0fb341 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -532,6 +532,7 @@ class ISACaller:
             illegal = name != asmop
 
         if illegal:
+            print ("name %s != %s - calling ILLEGAL trap" % (name, asmop))
             self.TRAP(0x700, PI.ILLEG)
             self.namespace['NIA'] = self.trap_nia
             self.pc.update(self.namespace)
diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index ee09d9ec..8c68e7fc 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -167,9 +167,8 @@ class TrapMainStage(PipeModBase):
             with m.Case(InternalOp.OP_MTMSRD):
                 L = self.fields.FormX.L[0:-1] # X-Form field L
                 with m.If(L):
-                    # just update EE and RI
-                    comb += msr_o.data[MSR.EE].eq(a_i[MSR.EE])
-                    comb += msr_o.data[MSR.RI].eq(a_i[MSR.RI])
+                    # just update RI..EE
+                    comb += msr_o.data[MSR.RI:MSR.EE].eq(a_i[MSR.RI:MSR.EE])
                 with m.Else():
                     # Architecture says to leave out bits 3 (HV), 51 (ME)
                     # and 63 (LE) (IBM bit numbering)
diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 6fbf960b..b53f935f 100644
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -107,6 +107,18 @@ class TrapTestCase(FHDLTestCase):
             initial_regs[2] = 1
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_3_mtmsr_0(self):
+        lst = ["mtmsr 1,0"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_2_mtmsr_1(self):
+        lst = ["mtmsr 1,1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        self.run_tst_program(Program(lst), initial_regs)
+
     def test_999_illegal(self):
         # ok, um this is a bit of a cheat: use an instruction we know
         # is not implemented by either ISACaller or the core