From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 23:42:19 +0000 (-0700)
Subject: In sat: 'x' in init attr should not override constant
X-Git-Tag: working-ls180~1085^2~51
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b37a093e95036b267481b2dae2046278eef4040;p=yosys.git

In sat: 'x' in init attr should not override constant
---

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index dd56d8c71..bcc690fa3 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -268,6 +268,8 @@ struct SatHelper
 				RTLIL::SigSpec removed_bits;
 				for (int i = 0; i < lhs.size(); i++) {
 					RTLIL::SigSpec bit = lhs.extract(i, 1);
+					if (bit.is_fully_const() && rhs[i] == State::Sx)
+						rhs[i] = bit;
 					if (!satgen.initial_state.check_all(bit)) {
 						removed_bits.append(bit);
 						lhs.remove(i, 1);
diff --git a/tests/sat/initval.v b/tests/sat/initval.v
index 5b661f8d6..d46ccae48 100644
--- a/tests/sat/initval.v
+++ b/tests/sat/initval.v
@@ -1,6 +1,7 @@
 module test(input clk, input [3:0] bar, output [3:0] foo);
   reg [3:0] foo = 0;
   reg [3:0] last_bar = 0;
+  reg [3:0] asdf = 4'b1xxx;
 
   always @*
     foo[1:0] <= bar[1:0];
@@ -11,5 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
   always @(posedge clk)
     last_bar <= bar;
 
+  always @*
+    asdf[2:0] <= 3'b111;
+
   assert property (foo == {last_bar[3:2], bar[1:0]});
 endmodule
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 2079d2f34..3d88aa971 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -1,4 +1,4 @@
 read_verilog -sv initval.v
-proc;;
+proc;
 
 sat -seq 10 -prove-asserts