From: Kevin Lim <ktlim@umich.edu>
Date: Tue, 28 Nov 2006 16:41:08 +0000 (-0500)
Subject: Remove assertion.  It's not needed and messes up writebacks when a 2 level cache... 
X-Git-Tag: m5_2.0_beta2~15^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b5fdf603399c63a9344206f1593b20fcb834013;p=gem5.git

Remove assertion.  It's not needed and messes up writebacks when a 2 level cache is used in a uniprocessor setting.

--HG--
extra : convert_revision : 020a9799cd7177fdb85a767701d6fcb8cf018827
---

diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index 5813a0281..ea615d70a 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -94,10 +94,6 @@ UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
 bool
 UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming)
 {
-    //Make sure we don't snoop a write
-    //we are expecting writeInvalidates on the snoop port of a uni-coherent cache
-    assert(!(!pkt->isInvalidate() && pkt->isWrite()));
-
     if (pkt->isInvalidate()) {
 /*  Temp Fix for now, forward all invalidates up as functional accesses */
         if (isTiming) {