From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 15 May 2023 19:47:02 +0000 (+0100)
Subject: found the location to cut/paste the disassembly extra from
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b60ad1a303817558f339e51549682b207863214;p=openpower-isa.git

found the location to cut/paste the disassembly extra from
https://bugs.libre-soc.org/show_bug.cgi?id=1084
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 9774b6c4..3a4bee10 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1493,12 +1493,12 @@ class ConditionRegisterFieldOperand(ExtendableOperand):
             yield f"{indent}{indent}{int(value):0{value.bits}b}"
             yield f"{indent}{indent}{', '.join(span)}"
             if isinstance(insn, SVP64Instruction):
-                extra_idx = self.extra_idx
-                if self.record.etype is _SVEType.NONE:
-                    yield f"{indent}{indent}extra[none]"
-                else:
-                    etype = repr(self.record.etype).lower()
-                    yield f"{indent}{indent}{etype}{extra_idx!r}"
+                for extra_idx in frozenset(self.extra_idx):
+                    if self.record.etype is _SVEType.NONE:
+                        yield f"{indent}{indent}extra[none]"
+                    else:
+                        etype = repr(self.record.etype).lower()
+                        yield f"{indent}{indent}{etype}{extra_idx!r}"
         else:
             vector = "*" if vector else ""
             CR = int(value >> 2)