From: Luke Kenneth Casson Leighton Date: Sat, 27 Jun 2020 18:43:00 +0000 (+0100) Subject: make PortInterface modules consistent with same API X-Git-Tag: div_pipeline~238 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b6bb745bfae2a04b41f8e0398775bb3065d7a75;p=soc.git make PortInterface modules consistent with same API --- diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index c974a82e..84f5f4be 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -244,7 +244,7 @@ class L0CacheBuffer(Elaboratable): with m.If(idx_l.q): comb += self.pimem.connect_port(port) - with m.If(~self.pimem.pi.pi.busy_o): + with m.If(~self.pimem.pi.busy_o): comb += reset_l.s.eq(1) # reset when no longer busy # ugly hack, due to simultaneous addr req-go acknowledge @@ -278,7 +278,7 @@ class TstL0CacheBuffer(Elaboratable): m.submodules.pimem = self.pimem m.submodules.l0 = self.l0 if hasattr(self.cmpi, 'lsmem'): # hmmm not happy about this - dut.submodules.lsmem = self.cmpi.lsmem.lsi + m.submodules.lsmem = self.cmpi.lsmem.lsi return m @@ -341,7 +341,7 @@ def l0_cache_st(dut, addr, data, datalen): # can go straight to reset. yield port1.is_st_i.eq(0) # end yield port1.addr.ok.eq(0) # set !ok - # yield from wait_busy(port1, False) # wait until not busy + yield from wait_busy(port1, False) # wait until not busy def l0_cache_ld(dut, addr, datalen, expected): @@ -368,7 +368,7 @@ def l0_cache_ld(dut, addr, datalen, expected): # cleanup yield port1.is_ld_i.eq(0) # end yield port1.addr.ok.eq(0) # set !ok - # yield from wait_busy(port1, no=False) # wait until not busy + yield from wait_busy(port1, no=False) # wait until not busy return data diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index e51d41e7..e52425d1 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -49,6 +49,9 @@ class Pi2LSUI(Elaboratable): """ return addr[:self.addrbits], addr[self.addrbits:] + def connect_port(self, inport): + return self.pi.connect_port(inport) + def elaborate(self, platform): m = Module() pi, lsui, addrbits = self.pi, self.lsui, self.addrbits diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 0d2e7784..9ebaa732 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -120,6 +120,21 @@ class PortInterface(RecordObject): self.ld = Data(regwid, "ld_data_o") # ok to be set by L0 Cache/Buf self.st = Data(regwid, "st_data_i") # ok to be set by CompUnit + def connect_port(self, inport): + print ("connect_port", self, inport) + return [self.is_ld_i.eq(inport.is_ld_i), + self.is_st_i.eq(inport.is_st_i), + self.data_len.eq(inport.data_len), + self.go_die_i.eq(inport.go_die_i), + self.addr.data.eq(inport.addr.data), + self.addr.ok.eq(inport.addr.ok), + self.st.eq(inport.st), + inport.ld.eq(self.ld), + inport.busy_o.eq(self.busy_o), + inport.addr_ok_o.eq(self.addr_ok_o), + inport.addr_exc_o.eq(self.addr_exc_o), + ] + class LDSTPort(Elaboratable): def __init__(self, idx, regwid=64, addrwid=48): @@ -210,7 +225,8 @@ class TestMemoryPortInterface(Elaboratable): init=False) self.regwid = regwid self.addrwid = addrwid - self.pi = LDSTPort(0, regwid, addrwid) + self.lpi = LDSTPort(0, regwid, addrwid) + self.pi = self.lpi.pi @property def addrbits(self): @@ -222,7 +238,7 @@ class TestMemoryPortInterface(Elaboratable): return addr[:self.addrbits], addr[self.addrbits:] def connect_port(self, inport): - return self.pi.connect_port(inport) + return self.lpi.connect_port(inport) def elaborate(self, platform): m = Module() @@ -232,7 +248,7 @@ class TestMemoryPortInterface(Elaboratable): m.submodules.mem = self.mem # connect the ports as modules - m.submodules.port0 = self.pi + m.submodules.port0 = self.lpi # state-machine latches m.submodules.st_active = st_active = SRLatch(False, name="st_active") @@ -245,7 +261,7 @@ class TestMemoryPortInterface(Elaboratable): lds = Signal(reset_less=True) sts = Signal(reset_less=True) - pi = self.pi.pi + pi = self.pi comb += lds.eq(pi.is_ld_i & pi.busy_o) # ld-req signals comb += sts.eq(pi.is_st_i & pi.busy_o) # st-req signals diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index f19fe9f9..339c6dc0 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -53,9 +53,10 @@ def sort_fuspecs(fuspecs): class NonProductionCore(Elaboratable): - def __init__(self, addrwid=6, idepth=16): + def __init__(self, addrwid=6, idepth=16, ifacetype='testpi'): # single LD/ST funnel for memory access - self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid) + self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, + addrwid=addrwid, ifacetype=ifacetype) pi = self.l0.l0.dports[0] # function units (only one each) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index e41bc652..b211a363 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -30,9 +30,9 @@ class TestIssuer(Elaboratable): efficiency and speed is not the main goal here: functional correctness is. """ - def __init__(self, addrwid=6, idepth=6): + def __init__(self, addrwid=6, idepth=6, ifacetype='testpi'): # main instruction core - self.core = core = NonProductionCore(addrwid) + self.core = core = NonProductionCore(addrwid, ifacetype=ifacetype) # Test Instruction memory self.imem = TestMemory(32, idepth) diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 0bd2b5ad..b6cc9f6e 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -56,7 +56,7 @@ class TestRunner(FHDLTestCase): go_insn_i = Signal() pc_i = Signal(32) - m.submodules.issuer = issuer = TestIssuer() + m.submodules.issuer = issuer = TestIssuer(ifacetype="test_bare_wb") imem = issuer.imem.mem core = issuer.core pdecode2 = core.pdecode2