From: Jean-François Nguyen <jf@lambdaconcept.com>
Date: Mon, 28 Jun 2021 14:18:10 +0000 (+0200)
Subject: periph.serial: use buffered FIFOs to help BRAM inference.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b77f7fea2346e9e9d69b943defc68a05563cd65;p=lambdasoc.git

periph.serial: use buffered FIFOs to help BRAM inference.
---

diff --git a/lambdasoc/periph/serial.py b/lambdasoc/periph/serial.py
index 5176c13..a25c78d 100644
--- a/lambdasoc/periph/serial.py
+++ b/lambdasoc/periph/serial.py
@@ -1,5 +1,5 @@
 from nmigen import *
-from nmigen.lib.fifo import SyncFIFO
+from nmigen.lib.fifo import SyncFIFOBuffered
 
 from nmigen_stdio.serial import AsyncSerial
 
@@ -65,9 +65,9 @@ class AsyncSerialPeripheral(Peripheral, Elaboratable):
     def __init__(self, *, rx_depth=16, tx_depth=16, **kwargs):
         super().__init__()
 
-        self._phy       = AsyncSerial(**kwargs)
-        self._rx_fifo   = SyncFIFO(width=self._phy.rx.data.width, depth=rx_depth)
-        self._tx_fifo   = SyncFIFO(width=self._phy.tx.data.width, depth=tx_depth)
+        self._phy       = AsyncSerial(data_bits=data_bits, **kwargs)
+        self._rx_fifo   = SyncFIFOBuffered(width=self._phy.rx.data.width, depth=rx_depth)
+        self._tx_fifo   = SyncFIFOBuffered(width=self._phy.tx.data.width, depth=tx_depth)
 
         bank            = self.csr_bank()
         self._divisor   = bank.csr(self._phy.divisor.width, "rw")