From: lkcl Date: Fri, 1 Jan 2021 20:57:55 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~658 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b782c8e68d48b50010ce16e22079459b38d58df;p=libreriscv.git --- diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn new file mode 100644 index 000000000..fab0658ba --- /dev/null +++ b/openpower/sv/propagation.mdwn @@ -0,0 +1,6 @@ +# SV Context Propagation + +[[sv/svp64]] context is 24 bits long, and Swizzle is 12. These are enormous and not sustainable as far as power consumption is concerned. Also, there is repetition of the same contexts to different instructions. An idea therefore is to add a level of indirection that allows these contexts to be applied to multiple instructions. + +The basic principle is to have a special instruction in an svp64 context that takes a copy of the `RM[0..23]` bits, alongside a 16 bit suite of bits that indicates which of the following 16 32 bit instructions will have that `RM` applied to them. +