From: Luke Kenneth Casson Leighton Date: Sun, 4 Oct 2020 18:11:32 +0000 (+0100) Subject: significant reorg of the litex pinspecs to use pinmux JSON files X-Git-Tag: 24jan2021_ls180~245 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b82f31334a15796fc5f350b3e3722ffe63ff836;p=soc.git significant reorg of the litex pinspecs to use pinmux JSON files --- diff --git a/pinmux b/pinmux index 6e6f3a7e..429707cc 160000 --- a/pinmux +++ b/pinmux @@ -1 +1 @@ -Subproject commit 6e6f3a7e47ee08773d9ec0d8f129906ab28d140c +Subproject commit 429707cc3e1477608be1dfa97341831b77ba1e07 diff --git a/src/soc/config/pinouts.py b/src/soc/config/pinouts.py index 95713e05..d152d00e 100644 --- a/src/soc/config/pinouts.py +++ b/src/soc/config/pinouts.py @@ -22,6 +22,28 @@ def _byteify(data, ignore_dicts = False): # if it's anything else, return it in its original form return data + +def get_pinspecs(chipname=None, subset=None): + chip = load_pinouts(chipname) + pinmap = chip['pins.map'] + specs = {} + for k, bus in chip['pins.specs'].items(): + k, num = k.lower().split(":") + name = '%s%s' % (k, num) + if subset is None or name in subset: + pins = [] + for pin in bus: + pin = pin.lower() + pname = '%s_%s' % (name, pin[:-1]) + if pname in pinmap: + newpin = pinmap[pname][2:] + newpin = '_'.join(newpin.split("_")[1:]) + pin = newpin + pin[-1] + pins.append(pin) + specs['%s%s' % (k, num)] = pins + return specs + + def load_pinouts(chipname=None): """load_pinouts - loads the JSON-formatted dictionary of a chip spec diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py index 45d4ee30..c7c96454 100644 --- a/src/soc/debug/jtag.py +++ b/src/soc/debug/jtag.py @@ -25,7 +25,7 @@ def dummy_pinset(): # sigh this needs to come from pinmux. gpios = [] for i in range(16): - gpios.append("gpio%d*" % i) + gpios.append("%d*" % i) return {'uart': ['tx+', 'rx-'], 'gpio': gpios, 'i2c': ['sda*', 'scl+']} diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index 54f103e9..38c8d008 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -5,7 +5,8 @@ from migen import ClockSignal, ResetSignal, Signal, Instance, Cat from litex.soc.interconnect import wishbone as wb from litex.soc.cores.cpu import CPU -from soc.debug.jtag import Pins, dummy_pinset # TODO move to suitable location +from soc.config.pinouts import get_pinspecs +from soc.debug.jtag import Pins from c4m.nmigen.jtag.tap import IOType from libresoc.ls180 import io @@ -61,8 +62,13 @@ def make_jtag_ioconn(res, pin, cpupads, iopads): name = "%s_%s" % (fn, pin) if iotype in (IOType.In, IOType.Out): - cpup = getattr(cpu, pin) - iop = getattr(io, pin) + if pin.isdigit(): + idx = int(pin) + cpup = cpu[idx] + iop = io[idx] + else: + cpup = getattr(cpu, pin) + iop = getattr(io, pin) if iotype == IOType.Out: # output from the pad is routed through C4M JTAG and so @@ -76,7 +82,7 @@ def make_jtag_ioconn(res, pin, cpupads, iopads): elif iotype == IOType.InTriOut: if fn == 'gpio': # sigh decode GPIO special-case - idx = int(pin[4:]) + idx = int(pin[1:]) else: idx = 0 cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx] @@ -228,11 +234,30 @@ class LibreSoC(CPU): self.pad_cm = ConstraintManager(self.padresources, []) self.cpupads = {} iopads = {} - for (periph, num) in [('uart', 0), ('gpio', 0), ('i2c', 0)]: - self.cpupads[periph] = platform.request(periph, num) - iopads[periph] = self.pad_cm.request(periph, num) - - p = Pins(dummy_pinset()) + litexmap = {} + subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1', + 'pwm', 'sd0'}#, 'sdr'} + for periph in subset: + origperiph = periph + num = None + if periph[-1].isdigit(): + periph, num = periph[:-1], int(periph[-1]) + print ("periph request", periph, num) + if periph == 'mspi': + if num == 0: + periph, num = 'spimaster', None + else: + periph, num = 'spisdcard', None + elif periph == 'mtwi': + periph = 'i2c' + elif periph == 'sd': + periph, num = 'sdcard', None + litexmap[origperiph] = (periph, num) + self.cpupads[origperiph] = platform.request(periph, num) + iopads[origperiph] = self.pad_cm.request(periph, num) + + pinset = get_pinspecs(subset=subset) + p = Pins(pinset) for pin in list(p): make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads) diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py index 3eb6adc5..c47cbea5 100644 --- a/src/soc/litex/florent/libresoc/ls180.py +++ b/src/soc/litex/florent/libresoc/ls180.py @@ -69,7 +69,7 @@ def io(): ), # SPI0: 4 pins - ("spi_master", 0, + ("spimaster", 0, Subsignal("clk", Pins("J1")), Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")), Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")), @@ -126,8 +126,7 @@ def io(): ), # PWM: 2 pins - ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")), - ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")), + ("pwm", 0, Pins("P1 P2"), IOStandard("LVCMOS33")), ] n_gpio = 16 diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 4a14b244..29d89122 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -433,16 +433,27 @@ class LibreSoCSim(SoCCore): self.add_csr("gpio") # SPI Master - self.submodules.spi_master = SPIMaster( - pads = platform.request("spi_master"), + print ("cpupadkeys", self.cpu.cpupads.keys()) + self.submodules.spimaster = SPIMaster( + pads = self.cpu.cpupads['mspi1'], data_width = 8, sys_clk_freq = sys_clk_freq, spi_clk_freq = 8e6, ) - self.add_csr("spi_master") + self.add_csr("spimaster") + + # SPI SDCard (1 wide) + spi_clk_freq = 400e3 + pads = self.cpu.cpupads['mspi0'] + spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq) + spisdcard.add_clk_divider() + setattr(self.submodules, 'spisdcard', spisdcard) + self.add_csr('spisdcard') # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins - self.comb += self.cpu.interrupt[12:16].eq(platform.request("eint")) + eintpads = self.cpu.cpupads['eint'] + print ("eintpads", eintpads) + self.comb += self.cpu.interrupt[12:16].eq(eintpads) # JTAG jtagpads = platform.request("jtag") @@ -462,20 +473,21 @@ class LibreSoCSim(SoCCore): self.sync += self.dummy[i].eq(self.nc[i] | self.cpu.interrupt[0]) # PWM + pwmpads = self.cpu.cpupads['pwm'] for i in range(2): name = "pwm%d" % i - setattr(self.submodules, name, PWM(platform.request("pwm", i))) + setattr(self.submodules, name, PWM(pwmpads[i])) self.add_csr(name) # I2C Master - i2c_core_pads = self.cpu.cpupads['i2c'] + i2c_core_pads = self.cpu.cpupads['mtwi'] self.submodules.i2c = I2CMaster(i2c_core_pads) self.add_csr("i2c") # SDCard ----------------------------------------------------- # Emulator / Pads - sdcard_pads = self.platform.request("sdcard") + sdcard_pads = self.cpu.cpupads['sd0'] # Core self.submodules.sdphy = SDPHY(sdcard_pads, @@ -791,7 +803,6 @@ def main(): if args.platform == 'ls180': soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, platform=args.platform) - soc.add_spi_sdcard() builder = Builder(soc, compile_gateware = True) builder.build(run = True) os.chdir("../") diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 86b1b304..fe0a18a1 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -32,7 +32,8 @@ from soc.config.test.test_loadstore import TestMemPspec from soc.config.ifetch import ConfigFetchUnit from soc.decoder.power_enums import MicrOp from soc.debug.dmi import CoreDebug, DMIInterface -from soc.debug.jtag import JTAG, dummy_pinset # TODO, full pinset +from soc.debug.jtag import JTAG +from soc.config.pinouts import get_pinspecs from soc.config.state import CoreState from soc.interrupts.xics import XICS_ICP, XICS_ICS from soc.bus.simple_gpio import SimpleGPIO @@ -83,7 +84,9 @@ class TestIssuerInternal(Elaboratable): # JTAG interface self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag' if self.jtag_en: - self.jtag = JTAG(dummy_pinset()) + subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1', + 'pwm', 'sd0'}#, 'sdr'} + self.jtag = JTAG(get_pinspecs(subset=subset)) # instruction go/monitor self.pc_o = Signal(64, reset_less=True)