From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 3 Jul 2012 17:04:44 +0000 (+0200)
Subject: framebuffer: make simulation easier
X-Git-Tag: 24jan2021_ls180~3113
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b8562492415e37d4547ec621c4c1dbbf3c71ee6;p=litex.git

framebuffer: make simulation easier
---

diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py
index 92965641..34a22a15 100644
--- a/milkymist/framebuffer/__init__.py
+++ b/milkymist/framebuffer/__init__.py
@@ -2,7 +2,7 @@ from migen.fhdl.structure import *
 from migen.flow.actor import *
 from migen.flow.network import *
 from migen.flow import plumbing
-from migen.actorlib import ala, misc, dma_asmi, structuring
+from migen.actorlib import ala, misc, dma_asmi, structuring, sim
 from migen.bank.description import *
 from migen.bank import csrgen
 
@@ -202,6 +202,12 @@ class FIFO(Actor):
 			],
 			instances=[asfifo])
 
+def sim_fifo_gen():
+	while True:
+		t = sim.Token("dac")
+		yield t
+		print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"]))
+
 class FakeDMA(Actor):
 	def __init__(self, port):
 		self.port = port
@@ -222,7 +228,7 @@ class FakeDMA(Actor):
 		return Fragment(comb, sync)
 
 class Framebuffer:
-	def __init__(self, address, asmiport):
+	def __init__(self, address, asmiport, simulation=False):
 		asmi_bits = asmiport.hub.aw
 		alignment_bits = bits_for(asmiport.hub.dw//8) - 1
 		length_bits = _hbits + _vbits + 2 - alignment_bits
@@ -238,7 +244,10 @@ class Framebuffer:
 		cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
 		unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
 		vtg = ActorNode(VTG())
-		fifo = ActorNode(FIFO())
+		if simulation:
+			fifo = ActorNode(sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout)))
+		else:
+			fifo = ActorNode(FIFO())
 		
 		g = DataFlowGraph()
 		g.add_connection(fi, adrloop, source_subr=["length"])
@@ -258,17 +267,20 @@ class Framebuffer:
 		self.bank = csrgen.Bank(fi.actor.get_registers(), address=address)
 		
 		# VGA clock input
-		self.vga_clk = fifo.actor.vga_clk
+		if not simulation:
+			self.vga_clk = fifo.actor.vga_clk
 		
 		# Pads
 		self.vga_psave_n = Signal()
-		self.vga_hsync_n = fifo.actor.vga_hsync_n
-		self.vga_vsync_n = fifo.actor.vga_vsync_n
+		if not simulation:
+			self.vga_hsync_n = fifo.actor.vga_hsync_n
+			self.vga_vsync_n = fifo.actor.vga_vsync_n
 		self.vga_sync_n = Signal()
 		self.vga_blank_n = Signal()
-		self.vga_r = fifo.actor.vga_r
-		self.vga_g = fifo.actor.vga_g
-		self.vga_b = fifo.actor.vga_b
+		if not simulation:
+			self.vga_r = fifo.actor.vga_r
+			self.vga_g = fifo.actor.vga_g
+			self.vga_b = fifo.actor.vga_b
 
 	def get_fragment(self):
 		comb = [
diff --git a/tb/framebuffer/framebuffer.py b/tb/framebuffer/framebuffer.py
new file mode 100644
index 00000000..b12cf679
--- /dev/null
+++ b/tb/framebuffer/framebuffer.py
@@ -0,0 +1,34 @@
+from migen.fhdl.structure import *
+from migen.bus import asmibus
+from migen.sim.generic import Simulator, TopLevel
+from migen.sim.icarus import Runner
+
+from milkymist.framebuffer import *
+
+def main():
+	hub = asmibus.Hub(16, 128)
+	port = hub.get_port()
+	hub.finalize()
+	
+	dut = Framebuffer(1, port, True)
+	
+	fragment = hub.get_fragment() + dut.get_fragment()
+	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+	
+	sim.run(1)
+	def csr_w(addr, d):
+		sim.wr(dut.bank.description[addr].field.storage, d)
+	csr_w(1, 2) # hres
+	csr_w(2, 3) # hsync_start
+	csr_w(3, 4) # hsync_stop
+	csr_w(4, 5) # hscan
+	csr_w(5, 2) # vres
+	csr_w(6, 3) # vsync_start
+	csr_w(7, 4) # vsync_stop
+	csr_w(8, 5) # vscan
+	csr_w(10, 2*2*4) # length
+	csr_w(0, 1) # enable
+	
+	sim.run(200)
+
+main()