From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 19:28:19 +0000 (-0700)
Subject: Stop topological sort at abc_flop_q
X-Git-Tag: working-ls180~1237^2~209
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b860809e9dae557a435f01a3125e6dd4b4a8599;p=yosys.git

Stop topological sort at abc_flop_q
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ed0fc656f..070d6d403 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -180,14 +180,20 @@ struct XAigerWriter
 			toposort.node(cell->name);
 			for (const auto &conn : cell->connections())
 			{
-				// HACK!!!
-				if (cell->type.in("\\SB_DFF", "\\SB_DFFE", "\\SB_DFFESR", "\\SB_DFFSR", "\\SB_DFFESS") && conn.first.in("\\Q"))
-					continue;
+				if (!cell->type.in("$_NOT_", "$_AND_")) {
+					if (yosys_celltypes.cell_known(cell->type)) {
+						if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
+							continue;
+						if (cell->type == "$memrd" && conn.first == "\\DATA")
+							continue;
+					}
 
-				if (yosys_celltypes.cell_known(cell->type)) {
-					if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
-						continue;
-					if (cell->type == "$memrd" && conn.first == "\\DATA")
+					RTLIL::Module* inst_module = module->design->module(cell->type);
+					log_assert(inst_module);
+					RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
+					log_assert(inst_module_port);
+
+					if (inst_module_port->attributes.count("\\abc_flop_q"))
 						continue;
 				}