From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 Apr 2022 21:32:32 +0000 (+0100)
Subject: add tempfile to uart16550 wrapper which defines DATA_BUS_WIDTH_8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b8f22c9caefd4238b26c1c9cfcfecc4372df262;p=soc.git

add tempfile to uart16550 wrapper which defines DATA_BUS_WIDTH_8
---

diff --git a/src/soc/bus/uart_16550.py b/src/soc/bus/uart_16550.py
index 366696e9..bceec5e2 100644
--- a/src/soc/bus/uart_16550.py
+++ b/src/soc/bus/uart_16550.py
@@ -13,6 +13,7 @@ from nmigen import (Elaboratable, Cat, Module, Signal, ClockSignal, Instance,
 from nmigen_soc.wishbone.bus import Interface
 from nmigen.cli import rtlil, verilog
 import os
+import tempfile
 
 __all__ = ["UART16550"]
 
@@ -63,6 +64,13 @@ class UART16550(Elaboratable):
 
     @classmethod
     def add_verilog_source(cls, verilog_src_dir, platform):
+        # create a temp file containing "`define DATA_BUS_WIDTH_8"
+        t = tempfile.NamedTemporaryFile(delete=False, suffix=".v")
+        t.write("`define DATA_BUS_WIDTH_8\n".encode())
+        t.flush()
+        t.seek(0)
+        platform.add_file(t.name, t)
+
         # add each of the verilog sources, needed for when doing platform.build
         for fname in ['raminfr.v', 'uart_defines.v', 'uart_rfifo.v',
                       'uart_top.v', 'timescale.v', 'uart_receiver.v',