From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Sat, 27 Aug 2022 13:07:05 +0000 (+0000)
Subject: opcodes/riscv-dis.c: Tidying with comments/clarity
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b8fd83908ea61d9fb2215de5eb585870658fa89;p=binutils-gdb.git

opcodes/riscv-dis.c: Tidying with comments/clarity

Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

First, we need to clarify the roles of variables and code portions.

opcodes/ChangeLog:

	* riscv-dis.c (xlen): Move before default_isa_spec. Add comment.
	(default_isa_spec, default_priv_spec): Add comment.
	(riscv_gpr_names, riscv_fpr_names): Likewise.
	(parse_riscv_dis_option_without_args): Likewise.
	(parse_riscv_dis_option, parse_riscv_dis_options): Likewise.
	(maybe_print_address): Likewise.
	(riscv_disassemble_insn): Fix comment about the Zfinx "extension".
	Add comment about the riscv_multi_subset_supports call.
---

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 27a6bfe2283..2d1faf26eb3 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -32,10 +32,15 @@
 #include <stdint.h>
 #include <ctype.h>
 
+/* Current XLEN for the disassembler.  */
+unsigned xlen = 0;
+
+/* Default ISA specification version (constant as of now).  */
 static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1;
-static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
 
-unsigned xlen = 0;
+/* Default privileged specification
+   (as specified by the ELF attributes or the `priv-spec' option).  */
+static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
 
 static riscv_subset_list_t riscv_subsets;
 static riscv_parse_subset_t riscv_rps_dis =
@@ -61,12 +66,16 @@ static int last_map_symbol = -1;
 static bfd_vma last_stop_offset = 0;
 enum riscv_seg_mstate last_map_state;
 
+/* Register names as used by the disassembler.  */
 static const char * const *riscv_gpr_names;
 static const char * const *riscv_fpr_names;
 
 /* If set, disassemble as most general instruction.  */
 static int no_aliases;
 
+
+/* Set default RISC-V disassembler options.  */
+
 static void
 set_default_riscv_dis_options (void)
 {
@@ -75,6 +84,8 @@ set_default_riscv_dis_options (void)
   no_aliases = 0;
 }
 
+/* Parse RISC-V disassembler option (without arguments).  */
+
 static bool
 parse_riscv_dis_option_without_args (const char *option)
 {
@@ -90,6 +101,8 @@ parse_riscv_dis_option_without_args (const char *option)
   return true;
 }
 
+/* Parse RISC-V disassembler option (possibly with arguments).  */
+
 static void
 parse_riscv_dis_option (const char *option)
 {
@@ -143,6 +156,8 @@ parse_riscv_dis_option (const char *option)
     }
 }
 
+/* Parse RISC-V disassembler options.  */
+
 static void
 parse_riscv_dis_options (const char *opts_in)
 {
@@ -170,6 +185,8 @@ arg_print (struct disassemble_info *info, unsigned long val,
   (*info->fprintf_styled_func) (info->stream, dis_style_text, "%s", s);
 }
 
+/* If we need to print an address, set its value and state.  */
+
 static void
 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
 		     int wide)
@@ -697,7 +714,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	  xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
 	}
 
-      /* If arch has ZFINX flags, use gpr for disassemble.  */
+      /* If arch has the Zfinx extension, replace FPR with GPR.  */
       if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
 	riscv_fpr_names = riscv_gpr_names;
 
@@ -712,7 +729,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	  /* Is this instruction restricted to a certain value of XLEN?  */
 	  if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
 	    continue;
-
+	  /* Is this instruction supported by the current architecture?  */
 	  if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class))
 	    continue;