From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 28 Oct 2022 12:23:42 +0000 (+0100)
Subject: overflow condition in dsld and dsrd if RS is non-zero
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2b97853c8113b55d0dff54e5a6ee9bf5dda3ca5f;p=openpower-isa.git

overflow condition in dsld and dsrd if RS is non-zero
---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index e8232c27..6d82b896 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -60,6 +60,9 @@ Pseudo-code:
     mask <- MASK(64, 63-n)
     RT <- (v[0:63] & mask) | ((RC) & ¬mask)
     RS <- v[0:63] & ¬mask
+    overflow = 0
+    if RS != [0]*64:
+        overflow = 1
 
 Special Registers Altered:
 
@@ -79,6 +82,9 @@ Pseudo-code:
     mask <- MASK(n, 63)
     RT <- (v[0:63] & mask) | ((RC) & ¬mask)
     RS <- v[0:63] & ¬mask
+    overflow = 0
+    if RS != [0]*64:
+        overflow = 1
 
 Special Registers Altered: