From: lkcl <lkcl@web>
Date: Thu, 9 Jun 2022 16:37:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1889
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ba183f9945394a26dbec60a0ede94d69ecca800;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index e49e6152c..b33a13368 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -146,15 +146,15 @@ how many registers are to be considered Indices.
 
 mi0-2 and mo0-1 each select SVSHAPE0-3 to apply to a given register.
 mi0-2 apply to RA, RB, RC respectively, as input registers, and
-likewise mo0-1 apply to output registers (FRT, FRS respectively).
-SVme is 5 bits, and indicates indicate whether the
+likewise mo0-1 apply to output registers (RT/FRT, RS/FRS) respectively.
+SVme is 5 bits (one for each of mi0-2/mo0-1) and indicates whether the
 SVSHAPE is actively applied or not.
 
 * bit 0 of SVme indicates if mi0 is applied to RA / FRA
 * bit 1 of SVme indicates if mi1 is applied to RB / FRB
 * bit 2 of SVme indicates if mi2 is applied to RC / FRC
 * bit 3 of SVme indicates if mo0 is applied to RT / FRT
-* bit 4 of SVme indicates if mo1 is applied to Effective Address / FRS
+* bit 4 of SVme indicates if mo1 is applied to Effective Address / FRS / RS
   (LD/ST-with-update has an implicit 2nd write register, RA)
 
 # svremap instruction