From: Megan Wachs Date: Thu, 20 Jul 2017 21:53:34 +0000 (-0700) Subject: gpio: Add missing file X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2bad829e6e722412dc6de726f1617dafdb658a1b;p=sifive-blocks.git gpio: Add missing file --- diff --git a/src/main/scala/devices/gpio/GPIOPins.scala b/src/main/scala/devices/gpio/GPIOPins.scala new file mode 100644 index 0000000..11723c4 --- /dev/null +++ b/src/main/scala/devices/gpio/GPIOPins.scala @@ -0,0 +1,27 @@ +// See LICENSE for license details. +package sifive.blocks.devices.gpio + +import Chisel._ +import sifive.blocks.devices.pinctrl.{Pin} + +// While this is a bit pendantic, it keeps the GPIO +// device more similar to the other devices. It's not 'special' +// even though it looks like something that more directly talks to +// a pin. It also makes it possible to change the exact +// type of pad this connects to. +class GPIOPins[T <: Pin] (pingen: ()=> T, c: GPIOParams) extends Bundle { + + val pins = Vec(c.width, pingen()) + + override def cloneType: this.type = + this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] + + def fromGPIOPort(port: GPIOPortIO){ + + // This will just match up the components of the Bundle that + // exist in both. + (pins zip port.pins) foreach {case (pin, port) => + pin <> port + } + } +}