From: Marcin Kościelnicki <koriakin@0x04.net>
Date: Fri, 29 Nov 2019 15:55:29 +0000 (+0000)
Subject: xilinx: Add missing blackbox cell for BUFPLL.
X-Git-Tag: working-ls180~940^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2badaa9adbf3fa976ac7e9d967e7d098de429bed;p=yosys.git

xilinx: Add missing blackbox cell for BUFPLL.
---

diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 82e403f78..01e7101d1 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -372,6 +372,7 @@ CELLS = [
     Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
     Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
     Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}),
     Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}),
 
     # Clock buffers (IO and regional) -- Virtex.
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 671d16e8a..00a8a5f8a 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -5240,9 +5240,13 @@ module RAMB18E1 (...);
     parameter IS_RSTRAMB_INVERTED = 1'b0;
     parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
     parameter IS_RSTREGB_INVERTED = 1'b0;
+    (* abc9_arrival=2454 *)
     output [15:0] DOADO;
+    (* abc9_arrival=2454 *)
     output [15:0] DOBDO;
+    (* abc9_arrival=2454 *)
     output [1:0] DOPADOP;
+    (* abc9_arrival=2454 *)
     output [1:0] DOPBDOP;
     (* clkbuf_sink *)
     (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
@@ -5452,9 +5456,13 @@ module RAMB36E1 (...);
     parameter IS_RSTREGB_INVERTED = 1'b0;
     output CASCADEOUTA;
     output CASCADEOUTB;
+    (* abc9_arrival=2454 *)
     output [31:0] DOADO;
+    (* abc9_arrival=2454 *)
     output [31:0] DOBDO;
+    (* abc9_arrival=2454 *)
     output [3:0] DOPADOP;
+    (* abc9_arrival=2454 *)
     output [3:0] DOPBDOP;
     output [7:0] ECCPARITY;
     output [8:0] RDADDRECC;
@@ -8527,6 +8535,18 @@ module BUFIO2FB (...);
     input I;
 endmodule
 
+module BUFPLL (...);
+    parameter integer DIVIDE = 1;
+    parameter ENABLE_SYNC = "TRUE";
+    (* clkbuf_driver *)
+    output IOCLK;
+    output LOCK;
+    output SERDESSTROBE;
+    input GCLK;
+    input LOCKED;
+    input PLLIN;
+endmodule
+
 module BUFPLL_MCB (...);
     parameter integer DIVIDE = 2;
     parameter LOCK_SRC = "LOCK_TO_0";