From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Mon, 10 Jan 2022 23:20:26 +0000 (+0000)
Subject: Adding JTAG test info
X-Git-Tag: opf_rfc_ls005_v1~3263
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2bcb4f09b1b8c382f00f4958ae0bbea177653405;p=libreriscv.git

Adding JTAG test info
---

diff --git a/docs/pinmux/temp_pinmux_info.mdwn b/docs/pinmux/temp_pinmux_info.mdwn
index 9ca37b651..bc7daa16e 100644
--- a/docs/pinmux/temp_pinmux_info.mdwn
+++ b/docs/pinmux/temp_pinmux_info.mdwn
@@ -77,26 +77,44 @@ the Boundary Scan chain is extended. The JTAG module then provides subsignals
 to connect to core as well as pad side.
 
 I2C and UART are connected in a loopback configuration (input to output), 
-allowing to test both signals at the same time. The GPIO output is an XOR of the GPIO input, and a test input controlled by sim (gpio_o_test). The oe signals are controlled by the sim using test input registers. 
+allowing to test both signals at the same time. The GPIO output is an XOR of 
+the GPIO input, and a test input controlled by sim (gpio_o_test). 
+The oe signals are controlled by the sim using test input registers. 
 
 ## ASIC Platform
 Performs some magic with file template code.
-Resource list (dummy pinset) provided at instantiation is added to the internal resource list (?).
+Resource list (dummy pinset) provided at instantiation is added to the internal 
+resource list (?).
 More magic with configuring pins that are inputs/outputs/tristates.
 Core/Pad pins are connected to the appropriate JTAG pins.
 
 ## Unit tests
 ### GPIO test
-For every output configuration of four GPIOs (16), go through each input configuration. Assert that signal states match the function in the Blinker class.
+For every output configuration of four GPIOs (16), go through each input 
+configuration. 
+Assert that signal states match the function in the Blinker class.
 
 ### UART test
 Check TX matches RX when high and low.
 
 ### I2C test
-Check SDA out and SCL out match SDA/SCL in. Check oe's by driving the test registers.
-
-### JTAG tests
-TODO
+Check SDA out and SCL out match SDA/SCL in. 
+Check oe's by driving the test registers.
+
+### JTAG test BS chain
+The unit test has four test cases, two before the peripherals are exercised, 
+and two after:
+1. Send 0xFFFFF via TDI in EX_TEST mode
+1. Send 0xFFFFF via TDO in BS_SAMPLE mode
+1. Send 0x00000 via TDI in EX_TEST mode
+1. Send 0x00000 via TDI in BS_SAMPLE mode
+
+The expected results are:
+1. All core outputs high (as these set by JTAG BS), all pad inputs low
+(not asserted yet)
+1. All signals should be low (as JTAG TDI is ignored and all inputs low).
+1. All pad inputs and sim controlled input (output enables etc.) should be high.
+1. All signals should be high.
 
 # Simple GPIO extension
 The code from soc repo was taken and is being extended to support full gpio capability