From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 7 Jun 2020 19:40:44 +0000 (-0300)
Subject: Try responding with ready_i on the same cycle as valid_o
X-Git-Tag: div_pipeline~488
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2bd32dae2b77c8f65c008e3e7795bb2249244ddc;p=soc.git

Try responding with ready_i on the same cycle as valid_o
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index c2179cf9..0301d744 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -388,16 +388,17 @@ class BranchALU(Elaboratable):
         return list(self)
 
 def run_op(dut, a, b, op, inv_a=0):
+    from nmigen.back.pysim import Settle
     yield dut.a.eq(a)
     yield dut.b.eq(b)
     yield dut.op.insn_type.eq(op)
     yield dut.op.invert_a.eq(inv_a)
     yield dut.n.ready_i.eq(0)
     yield dut.p.valid_i.eq(1)
-    yield
 
     # if valid_o rose on the very first cycle, it is a
     # zero-delay ALU
+    yield Settle()
     vld = yield dut.n.valid_o
     if vld:
         # special case for zero-delay ALU
@@ -412,6 +413,8 @@ def run_op(dut, a, b, op, inv_a=0):
         yield
         return result
 
+    yield
+
     # wait for the ALU to accept our input data
     while True:
         rdy = yield dut.p.ready_o
@@ -423,6 +426,7 @@ def run_op(dut, a, b, op, inv_a=0):
 
     # wait for the ALU to present the output data
     while True:
+        yield Settle()
         vld = yield dut.n.valid_o
         if vld:
             break