From: lkcl <lkcl@web>
Date: Mon, 15 Aug 2022 15:06:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~856
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2bd95b1e65a672ced891ca8fe5f2903756df981a;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 79dfbe34f..afe311f56 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -231,3 +231,19 @@ loop:
     end:
       blr
 
+## Load/Store-Multi (selective)
+
+Up to 64 FPRs will be loaded, here.  `r3` is set one per bit
+for each FP register required to be loaded.  The block of memory
+from which the registers are loaded is contiguous (no gaps):
+any FP register which has a corresponding zero bit in `r3`
+is *unaltered*.  In essence this is a selective LD-multi with
+"Scatter" capability.
+
+    setvli r0, MVL=64, VL=64
+    sv.fld/dm=r3 *r0, 0(r30) # selective load 64 FP registers
+
+Up to 64 FPRs will be saved, here.  Again, `r3` 
+
+    setvli r0, MVL=64, VL=64
+    sv.stfd/sm=r3 *fp0, 0(r30) # selective store 64 FP registers