From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 Date: Wed, 24 Feb 2021 00:38:32 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~126 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2be189b907bc5db1547fd78d1a2d1d6ffaddf14c;p=libreriscv.git --- diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn index 980e42a77..7f9875991 100644 --- a/HDL_workflow/ECP5_FPGA.mdwn +++ b/HDL_workflow/ECP5_FPGA.mdwn @@ -40,9 +40,9 @@ Now lets review all of the relevant material on this page before we begin the wi Next we will wire up the STLINKv2 and our FPGA in three separate stages. -* First we will attach the FEMALE end of a FEMALE-TO-MALE (FTM) jumper cable to each necessary header pin on the STLINKv2. +* First we will attach the FEMALE end of a ***FEMALE-TO-MALE (FTM)*** jumper cable to each necessary header pin on the STLINKv2. -* Then we will attach one end of a FEMALE-TO-FEMALE (FTF) cable to each male header pin on the FPGA. +* Then we will attach one end of a ***FEMALE-TO-FEMALE (FTF)*** cable to each male header pin on the FPGA. * Finally, we will connect the wires from the STLINKv2 to the wires from the FPGA by matching the colours of the wires.