From: Andreas Sandberg Date: Tue, 13 Jun 2017 10:28:17 +0000 (+0100) Subject: mem-cache: Add missing overrides to BaseCache X-Git-Tag: v19.0.0.0~2728 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2beb74355697034720562e5d4b6d16c12510eb4a;p=gem5.git mem-cache: Add missing overrides to BaseCache Change-Id: I6a3a57e3067c247bd6ce6f01ac9459883f4aae2c Signed-off-by: Andreas Sandberg Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/3880 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Maintainer: Nikos Nikoleris --- diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 2f4b934b3..431c2f84a 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -228,7 +228,7 @@ class BaseCache : public MemObject /** * Write back dirty blocks in the cache using functional accesses. */ - virtual void memWriteback() = 0; + virtual void memWriteback() override = 0; /** * Invalidates all blocks in the cache. * @@ -236,7 +236,7 @@ class BaseCache : public MemObject * memory. Make sure to call functionalWriteback() first if you * want the to write them to memory. */ - virtual void memInvalidate() = 0; + virtual void memInvalidate() override = 0; /** * Determine if there are any dirty blocks in the cache. * @@ -460,18 +460,18 @@ class BaseCache : public MemObject /** * Register stats for this object. */ - virtual void regStats(); + virtual void regStats() override; public: BaseCache(const BaseCacheParams *p, unsigned blk_size); ~BaseCache() {} - virtual void init(); + virtual void init() override; virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; virtual BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; /** * Query block size of a cache.