From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 28 Apr 2021 10:15:41 +0000 (+0000)
Subject: add vbe spblock models to non_generated and build scripts
X-Git-Tag: LS180_RC3~78^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2bf2f9225e5397f3a59775fdb09bfd61ded258c4;p=soclayout.git

add vbe spblock models to non_generated and build scripts
---

diff --git a/experiments9/build_full_4ksram.sh b/experiments9/build_full_4ksram.sh
index ef2257d..050c719 100755
--- a/experiments9/build_full_4ksram.sh
+++ b/experiments9/build_full_4ksram.sh
@@ -25,6 +25,7 @@ cp non_generated/full_core_4_4ksram_ls180.v ls180.v
 cp non_generated/full_core_4_4ksram_litex_ls180.v litex_ls180.v
 cp non_generated/full_core_4_4ksram_libresoc.v libresoc.v
 cp non_generated/spblock*.v .
+cp non_generated/spblock*.vbe .
 cp non_generated/pll.v .
 touch mem.init
 touch mem_1.init
diff --git a/experiments9/freepdk_c4m45/build_full.sh b/experiments9/freepdk_c4m45/build_full.sh
index 4b44222..ffc8e3e 100755
--- a/experiments9/freepdk_c4m45/build_full.sh
+++ b/experiments9/freepdk_c4m45/build_full.sh
@@ -27,6 +27,7 @@ cp non_generated/ls180.v ls180.v
 cp non_generated/litex_ls180.v litex_ls180.v
 cp non_generated/libresoc.v libresoc.v
 cp non_generated/spblock*.v .
+cp non_generated/spblock*.vbe .
 cp non_generated/pll.v .
 touch mem.init
 touch mem_1.init
diff --git a/experiments9/non_generated/SPBlock_512W64B8W.vbe b/experiments9/non_generated/SPBlock_512W64B8W.vbe
deleted file mode 100644
index c752468..0000000
--- a/experiments9/non_generated/SPBlock_512W64B8W.vbe
+++ /dev/null
@@ -1,19 +0,0 @@
-
--- Phony VHDL interface for SRAM block.
-
-entity SPBlock_512W64B8W is
-   port ( clk     : in  bit
-        ; we      : in  bit_vector( 7 downto 0)
-        ; a       : in  bit_vector( 8 downto 0)
-        ; d       : in  bit_vector(63 downto 0)
-        ; q       : out bit_vector(63 downto 0)
-        ; vdd     : in  bit
-        ; vss     : in  bit
-        );
-end SPBlock_512W64B8W;
-
-architecture behavioral of SPBlock_512W64B8W is
-
-begin
-
-end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w.vbe b/experiments9/non_generated/spblock512w64b8w.vbe
new file mode 100644
index 0000000..de2d3df
--- /dev/null
+++ b/experiments9/non_generated/spblock512w64b8w.vbe
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b8w;
+
+architecture behavioral of spblock512w64b8w is
+
+begin
+
+end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w_0.vbe b/experiments9/non_generated/spblock512w64b8w_0.vbe
new file mode 100644
index 0000000..a2ba9c5
--- /dev/null
+++ b/experiments9/non_generated/spblock512w64b8w_0.vbe
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w_0 is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b8w_0;
+
+architecture behavioral of spblock512w64b8w_0 is
+
+begin
+
+end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w_1.vbe b/experiments9/non_generated/spblock512w64b8w_1.vbe
new file mode 100644
index 0000000..40a2f77
--- /dev/null
+++ b/experiments9/non_generated/spblock512w64b8w_1.vbe
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b81_1 is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b81_1;
+
+architecture behavioral of spblock512w64b81_1 is
+
+begin
+
+end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w_2.vbe b/experiments9/non_generated/spblock512w64b8w_2.vbe
new file mode 100644
index 0000000..d14ef7f
--- /dev/null
+++ b/experiments9/non_generated/spblock512w64b8w_2.vbe
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w_2 is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b8w_2;
+
+architecture behavioral of spblock512w64b8w_2 is
+
+begin
+
+end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w_3.vbe b/experiments9/non_generated/spblock512w64b8w_3.vbe
new file mode 100644
index 0000000..164765c
--- /dev/null
+++ b/experiments9/non_generated/spblock512w64b8w_3.vbe
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w_3 is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b8w_3;
+
+architecture behavioral of spblock512w64b8w_3 is
+
+begin
+
+end behavioral;