From: Cesar Strauss <cestrauss@gmail.com>
Date: Wed, 17 Feb 2021 10:39:39 +0000 (-0300)
Subject: Setup SVSTATE, from the test settings, at the start
X-Git-Tag: convert-csv-opcode-to-binary~225
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2bf9a3753b60fa1591b893bfb61de39c210a7d67;p=soc.git

Setup SVSTATE, from the test settings, at the start
---

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index f3b43950..df720cf2 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -19,6 +19,7 @@ from soc.config.endian import bigendian
 
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
+from soc.regfile.regfiles import StateRegs
 
 from soc.simple.issuer import TestIssuerInternal
 
@@ -214,8 +215,9 @@ class TestRunner(FHDLTestCase):
                 yield from setup_i_memory(imem, pc, instructions)
                 yield from setup_test_memory(l0, sim)
                 yield from setup_regs(pdecode2, core, test)
-                # TODO, setup svstate here in core.regs.state regfile
-                # https://bugs.libre-soc.org/show_bug.cgi?id=583#c35
+                # setup of SVSTATE
+                svstate_reg = core.regs.state.regs[StateRegs.SVSTATE].reg
+                yield svstate_reg.eq(test.svstate.spr.value)
 
                 yield pc_i.eq(pc)
                 yield issuer.pc_i.ok.eq(1)