From: Tobias Platen <tplaten@posteo.de>
Date: Thu, 4 Feb 2021 20:01:38 +0000 (+0100)
Subject: src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
X-Git-Tag: convert-csv-opcode-to-binary~260
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c06167d6d3dc294596f7598904754cb8b3c2155;p=soc.git

src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
---

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 13a3810b..b5c95456 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -136,6 +136,7 @@ class FSMMMUStage(ControlBase):
         #self.debug1 = Signal(64)
         #self.debug2 = Signal(64)
         #self.debug3 = Signal(64)
+        self.illegal = Signal()
 
         # for SPR field number access
         i = self.p.data_i
@@ -222,10 +223,13 @@ class FSMMMUStage(ControlBase):
             # FIXME: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
 
             with m.Switch(op.insn_type):
-                comb += self.debug0.eq(3)
                 with m.Case(MicrOp.OP_MTSPR):
+                    comb += done.eq(1)
+                    comb += self.debug0.eq(3)
+                    """
                     # subset SPR: first check a few bits
                     with m.If(~spr[9] & ~spr[5]):
+                        comb += self.debug0.eq(3)
                         with m.If(spr[0]):
                             comb += dsisr.eq(a_i[:32])
                         with m.Else():
@@ -233,18 +237,23 @@ class FSMMMUStage(ControlBase):
                         comb += done.eq(1)
                     # pass it over to the MMU instead
                     with m.Else():
+                        comb += self.debug0.eq(4)
                         # blip the MMU and wait for it to complete
                         comb += valid.eq(1)   # start "pulse"
                         comb += l_in.valid.eq(blip)   # start
                         comb += l_in.mtspr.eq(1)      # mtspr mode
                         comb += l_in.sprn.eq(spr)  # which SPR
                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
-                        comb += done.eq(l_out.done) # zzzz
+                        comb += done.eq(1) # FIXME l_out.done
+                       """
 
                 with m.Case(MicrOp.OP_MFSPR):
-                    comb += self.debug0.eq(3)
+                    comb += done.eq(1)
+                    comb += self.debug0.eq(4)
+                    """
                     # subset SPR: first check a few bits
                     with m.If(~spr[9] & ~spr[5]):
+                        comb += self.debug0.eq(5)
                         with m.If(spr[0]):
                             comb += o.data.eq(dsisr)
                         with m.Else():
@@ -253,6 +262,7 @@ class FSMMMUStage(ControlBase):
                         comb += done.eq(1)
                     # pass it over to the MMU instead
                     with m.Else():
+                        comb += self.debug0.eq(6)
                         # blip the MMU and wait for it to complete
                         comb += valid.eq(1)   # start "pulse"
                         comb += l_in.valid.eq(blip)   # start
@@ -261,7 +271,8 @@ class FSMMMUStage(ControlBase):
                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
                         comb += o.data.eq(l_out.sprval) # SPR from MMU
                         comb += o.ok.eq(l_out.done) # only when l_out valid
-                        comb += done.eq(l_out.done) # zzzz
+                        comb += done.eq(1) # FIXME l_out.done
+                    """
 
                 with m.Case(MicrOp.OP_DCBZ):
                     # activate dcbz mode (spec: v3.0B p850)
@@ -284,6 +295,8 @@ class FSMMMUStage(ControlBase):
                     comb += l_in.addr.eq(b_i)  # incoming operand (RB)
                     comb += done.eq(l_out.done) # zzzz
                     comb += self.debug0.eq(2)
+                with m.Case(MicrOp.OP_ILLEGAL):
+                    comb += self.illegal.eq(1)
 
             with m.If(self.n.ready_i & self.n.valid_o):
                 m.d.sync += busy.eq(0)
diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 55da495b..2a45ec2d 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -331,7 +331,8 @@ class TestRunner(FHDLTestCase):
         if(self.microwatt_mmu):
             traces += [
                 {'comment': 'microwatt_mmu'},
-                'core.fus.mmu0.alu_mmu0.illegal'
+                'core.fus.mmu0.alu_mmu0.illegal',
+                'core.fus.mmu0.alu_mmu0.debug0[3:0]'
             ]
 
         write_gtkw("issuer_simulator.gtkw",