From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 5 Jun 2019 19:28:26 +0000 (-0700)
Subject: Call shregmap -tech xilinx_static
X-Git-Tag: working-ls180~1208^2~192
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c18d530ea69094e7ed46dcf781d8f2517d4c61e;p=yosys.git

Call shregmap -tech xilinx_static
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e825a032c..7686f2cbc 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -304,7 +304,7 @@ struct SynthXilinxPass : public ScriptPass
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
-				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
+				run("shregmap -tech xilinx_static -minlen 3", "(skip if '-nosrl')");
 			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}