From: Andrew Waterman Date: Mon, 13 Mar 2017 19:46:33 +0000 (-0700) Subject: RISC-V: Fix [dis]assembly of srai/srli X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c232b8361a044d689d12161b7a645d238586f5e;p=binutils-gdb.git RISC-V: Fix [dis]assembly of srai/srli These were simple copy/paste errors from the compressed left shift pattern, which can't have a 0-register. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f9f2c048deb..622ccf49c68 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2017-03-13 Andrew Waterman + + * riscv-opc.c (riscv_opcodes) : Use match_opcode. + Likewise. + Likewise. + Likewise. + 2017-03-09 H.J. Lu * i386-gen.c (opcode_modifiers): Replace S with Load. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 61d01596183..1bb90ee13ea 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -210,14 +210,14 @@ const struct riscv_opcode riscv_opcodes[] = {"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, {"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, {"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, -{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS }, {"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, -{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS }, {"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, {"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, -{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS }, {"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, -{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS }, {"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, {"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, {"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },