From: Luke Kenneth Casson Leighton Date: Sun, 31 May 2020 16:44:03 +0000 (+0100) Subject: remove unneeded imports X-Git-Tag: div_pipeline~712 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c26d7f82187f1a8dda14704019d17171e439281;p=soc.git remove unneeded imports --- diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index c10e9584..350b4b82 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -10,13 +10,12 @@ its result(s) have been successfully stored in the regfile(s) Documented at http://libre-soc.org/3d_gpu/architecture/compunit """ -from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Cat, Const +from nmigen import Module, Signal, Mux, Elaboratable, Repl, Cat, Const from nmigen.hdl.rec import (Record, DIR_FANIN, DIR_FANOUT) from nmutil.latch import SRLatch, latchregister from nmutil.iocontrol import RecordObject -from soc.decoder.power_decoder2 import Data from soc.fu.regspec import RegSpec, RegSpecALUAPI diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index f0873ba6..f794ad98 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -11,16 +11,10 @@ Documented at http://libre-soc.org/3d_gpu/architecture/compunit """ from nmigen.compat.sim import run_simulation, Settle -from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Cat, Const -from nmigen.hdl.rec import (Record, DIR_FANIN, DIR_FANOUT) +from nmigen.cli import rtlil +from nmigen import Module -from nmutil.latch import SRLatch, latchregister -from nmutil.iocontrol import RecordObject - -from soc.decoder.power_decoder2 import Data from soc.decoder.power_enums import InternalOp -from soc.fu.regspec import RegSpec, RegSpecALUAPI from soc.experiment.compalu_multi import MultiCompUnit from soc.experiment.alu_hier import ALU, DummyALU