From: Christophe Monat Date: Tue, 24 Nov 2015 21:17:54 +0000 (+0100) Subject: [GAS, ARM] Invalid LDR immediate transformation X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c32be708da9011b3ce7404f2be43b17ab1eddd4;p=binutils-gdb.git [GAS, ARM] Invalid LDR immediate transformation 2015-11-24 Christophe Monat * config/tc-arm.c (move_or_literal_pool): Do not transform ldr ri,=imm into movs when ri is a high register in T1. 2015-11-24 Christophe Monat * gas/arm/thumb2_ldr_immediate_armv6t2.s: Added high register tests. * gas/arm/thumb2_ldr_immediate_armv6t2.d: Accounted for new test cases. * gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: New. * gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: New. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index bec87cf00f7..10770661edd 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2015-11-24 Christophe Monat + + * config/tc-arm.c (move_or_literal_pool): Do not transform ldr + ri,=imm into movs when ri is a high register in T1. + 2015-11-20 Nick Clifton * po/fr.po: Updated French translation. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 23c506de397..8ea1e8d8386 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -7839,7 +7839,8 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) { if (thumb_p) { - if ((v & ~0xFF) == 0) + /* This can be encoded only for a low register. */ + if ((v & ~0xFF) == 0 && (inst.operands[i].reg < 8)) { /* This can be done with a mov(1) instruction. */ inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index a38fc255e95..aae4691ecb3 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2015-11-24 Christophe Monat + + * gas/arm/thumb2_ldr_immediate_armv6t2.s: Added high register + tests. + * gas/arm/thumb2_ldr_immediate_armv6t2.d: Accounted for new test + cases. + * gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: New. + * gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: New. + 2015-11-24 Matthew Wahab * gas/arm/armv7e-m+fpv5-d16.d: Skip test for *-*-pe, *-wince-* and diff --git a/gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.d b/gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.d index 6897bcd2ff3..09c46a8f181 100644 --- a/gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.d +++ b/gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.d @@ -1,4 +1,4 @@ -# name: Ldr immediate on armv6 +# name: Ldr immediate on armv6t2 # as: -march=armv6t2 # objdump: -dr --prefix-addresses --show-raw-insn #skip: *-*-pe *-wince-* *-*-coff @@ -10,7 +10,13 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> f04f 2163 mov.w r1, #1660969728 .* 0[0-9a-f]+ <[^>]+> f04f 1151 mov.w r1, #5308497 .* 0[0-9a-f]+ <[^>]+> f44f 228e mov.w r2, #290816 .* -0[0-9a-f]+ <[^>]+> 4a01 ldr r2, \[pc, #4\] .* +0[0-9a-f]+ <[^>]+> 4a07 ldr r2, \[pc, #28\] .* 0[0-9a-f]+ <[^>]+> f241 32f1 movw r2, #5105 .* +0[0-9a-f]+ <[^>]+> f04f 3872 mov.w r8, #1920103026 .* +0[0-9a-f]+ <[^>]+> f04f 2863 mov.w r8, #1660969728 .* +0[0-9a-f]+ <[^>]+> f04f 1851 mov.w r8, #5308497 .* +0[0-9a-f]+ <[^>]+> f44f 298e mov.w r9, #290816 .* +0[0-9a-f]+ <[^>]+> f8df 9008 ldr.w r9, \[pc, #8\] .* +0[0-9a-f]+ <[^>]+> f241 39f1 movw r9, #5105 .* 0[0-9a-f]+ <[^>]+> 0000 .short 0x0000 0[0-9a-f]+ <[^>]+> ff320000 .word 0xff320000 diff --git a/gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.s b/gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.s index 22a50141ed3..4b94c91c667 100644 --- a/gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.s +++ b/gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.s @@ -9,4 +9,10 @@ thumb2_ldr: ldr r2,=0x00047000 ldr r2,=0xFF320000 ldr r2,=0x000013F1 + ldr r8,=0x72727272 + ldr r8,=0x63006300 + ldr r8,=0x00510051 + ldr r9,=0x00047000 + ldr r9,=0xFF320000 + ldr r9,=0x000013F1 .pool diff --git a/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d b/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d new file mode 100644 index 00000000000..55b5f17887f --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d @@ -0,0 +1,24 @@ +# name: Ldr small immediate high registers on armv6t2 +# as: -march=armv6t2 +# objdump: -dr --prefix-addresses --show-raw-insn +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> 2000[[:space:]]+movs[[:space:]]+r0, #0.* +0[0-9a-f]+ <[^>]+> 2108[[:space:]]+movs[[:space:]]+r1, #8.* +0[0-9a-f]+ <[^>]+> 2251[[:space:]]+movs[[:space:]]+r2, #81.* +0[0-9a-f]+ <[^>]+> 231f[[:space:]]+movs[[:space:]]+r3, #31.* +0[0-9a-f]+ <[^>]+> 242f[[:space:]]+movs[[:space:]]+r4, #47.* +0[0-9a-f]+ <[^>]+> 253f[[:space:]]+movs[[:space:]]+r5, #63.* +0[0-9a-f]+ <[^>]+> 2680[[:space:]]+movs[[:space:]]+r6, #128.* +0[0-9a-f]+ <[^>]+> 27ff[[:space:]]+movs[[:space:]]+r7, #255.* +0[0-9a-f]+ <[^>]+> f04f 0800[[:space:]]+mov\.w[[:space:]]+r8, #0.* +0[0-9a-f]+ <[^>]+> f04f 0908[[:space:]]+mov\.w[[:space:]]+r9, #8.* +0[0-9a-f]+ <[^>]+> f04f 0a51[[:space:]]+mov\.w[[:space:]]+sl, #81.* +0[0-9a-f]+ <[^>]+> f04f 0b1f[[:space:]]+mov\.w[[:space:]]+fp, #31.* +0[0-9a-f]+ <[^>]+> f04f 0c2f[[:space:]]+mov\.w[[:space:]]+ip, #47.* +0[0-9a-f]+ <[^>]+> f04f 0d3f[[:space:]]+mov\.w[[:space:]]+sp, #63.* +0[0-9a-f]+ <[^>]+> f04f 0e80[[:space:]]+mov\.w[[:space:]]+lr, #128.* +0[0-9a-f]+ <[^>]+> f04f 0fff[[:space:]]+mov\.w[[:space:]]+pc, #255.* diff --git a/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s b/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s new file mode 100644 index 00000000000..d2254101860 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s @@ -0,0 +1,24 @@ + .thumb + .syntax unified + .thumb_func +thumb2_ldr: + # These can be encoded into movs since constant is small + # And register can be encoded in 3 bits + ldr r0,=0x00 + ldr r1,=0x08 + ldr r2,=0x51 + ldr r3,=0x1F + ldr r4,=0x2F + ldr r5,=0x3F + ldr r6,=0x80 + ldr r7,=0xFF + # These shall be encoded into mov.w + # Since register cannot be encoded in 3 bits + ldr r8,=0x00 + ldr r9,=0x08 + ldr r10,=0x51 + ldr r11,=0x1F + ldr r12,=0x2F + ldr r13,=0x3F + ldr r14,=0x80 + ldr r15,=0xFF