From: Luke Kenneth Casson Leighton Date: Sun, 23 Aug 2020 14:18:54 +0000 (+0100) Subject: comment why litex sim mem map is altered X-Git-Tag: semi_working_ecp5~272^2~15 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c521a7053f5f7d8e77fd9076df5cf0cb7467963;p=soc.git comment why litex sim mem map is altered --- diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index 68be7702..9d407eec 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -58,7 +58,11 @@ class LibreSoCSim(SoCSDRAM): # ram_fname: "0x00000000", # }, "little") ram_init = get_mem_data(ram_fname, "little") + + # remap the main RAM to reset-start-address self.mem_map["main_ram"] = 0x00000000 + + # without sram nothing works, therefore move it to higher up self.mem_map["sram"] = 0x90000000