From: Tim Newsome <tim@sifive.com>
Date: Fri, 28 Oct 2016 21:01:42 +0000 (-0700)
Subject: Check for exception after reading a register.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c5e7256661837629ac23fbf5ee15e1f076a6cab;p=riscv-isa-sim.git

Check for exception after reading a register.
---

diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index dc60a3e..aeefb96 100644
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -636,14 +636,21 @@ class register_read_op_t : public operation_t
           return false;
 
         case 1:
-          gs.start_packet();
-          if (gs.xlen == 32) {
-            gs.send(gs.dr_read32(4));
-          } else {
-            gs.send(gs.dr_read(SLOT_DATA0));
+          {
+            unsigned result = gs.dr_read(SLOT_DATA_LAST);
+            if (result) {
+              gs.send_packet("E03");
+              return true;
+            }
+            gs.start_packet();
+            if (gs.xlen == 32) {
+              gs.send(gs.dr_read32(4));
+            } else {
+              gs.send(gs.dr_read(SLOT_DATA0));
+            }
+            gs.end_packet();
+            return true;
           }
-          gs.end_packet();
-          return true;
       }
       return false;
     }