From: Andrea Corallo <andrea.corallo@arm.com>
Date: Thu, 17 Sep 2020 16:17:52 +0000 (+0100)
Subject: aarch64: Do not alter value on a force_reg returned rtx expanding __jcvt
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c62952f8160bdc8d4111edb34a4bc75096c1e05;p=gcc.git

aarch64: Do not alter value on a force_reg returned rtx expanding __jcvt

2020-09-17  Andrea Corallo  <andrea.corallo@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_general_expand_builtin): Use expand machinery not to
	alter the value of an rtx returned by force_reg.
---

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 2f4753b25cc..1cfb5c07d70 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -2140,14 +2140,14 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target,
       return target;
 
     case AARCH64_JSCVT:
-      arg0 = CALL_EXPR_ARG (exp, 0);
-      op0 = force_reg (DFmode, expand_normal (arg0));
-      if (!target)
-	target = gen_reg_rtx (SImode);
-      else
-	target = force_reg (SImode, target);
-      emit_insn (GEN_FCN (CODE_FOR_aarch64_fjcvtzs) (target, op0));
-      return target;
+      {
+	expand_operand ops[2];
+	create_output_operand (&ops[0], target, SImode);
+	op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+	create_input_operand (&ops[1], op0, DFmode);
+	expand_insn (CODE_FOR_aarch64_fjcvtzs, 2, ops);
+	return ops[0].value;
+      }
 
     case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF:
     case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF: