From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 20:32:09 +0000 (-0700)
Subject: Add test
X-Git-Tag: working-ls180~1219^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c6aaef3db87fe7955eded675fac452705e5cd48;p=yosys.git

Add test
---

diff --git a/tests/various/script.ys b/tests/various/script.ys
new file mode 100644
index 000000000..6044ad9b3
--- /dev/null
+++ b/tests/various/script.ys
@@ -0,0 +1,17 @@
+read_verilog -formal <<EOT
+    module top;
+        foo bar();
+        foo asdf();
+        winnie the_pooh();
+
+        wire [1023:0] _RUNME0 = "select -assert-count 2 t:foo";
+        wire [1023:0] _RUNME1 = "select -assert-count 1 t:winnie";
+        wire [1023:0] _DELETE = "delete c:bar";
+    endmodule
+EOT
+
+script -select w:_RUNME*
+
+select w:_DELETE
+script -select
+select -assert-count 1 t:foo