From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 29 Mar 2019 21:40:22 +0000 (+0000)
Subject: create FPDecode module
X-Git-Tag: ls180-24jan2020~1366
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c7486cb4389dd8a805487bec9008fd1e0d78383;p=ieee754fpu.git

create FPDecode module
---

diff --git a/src/add/fpadd/specialcases.py b/src/add/fpadd/specialcases.py
index 49e05089..06321117 100644
--- a/src/add/fpadd/specialcases.py
+++ b/src/add/fpadd/specialcases.py
@@ -6,7 +6,7 @@ from nmigen import Module, Signal, Cat, Const
 from nmigen.cli import main, verilog
 from math import log
 
-from fpbase import FPNumIn
+from fpbase import FPNumDecode
 from singlepipe import UnbufferedPipeline, StageChain
 
 from fpbase import FPState, FPID
@@ -47,12 +47,12 @@ class FPAddSpecialCasesMod:
         m.submodules.sc_out_z = self.o.z
 
         # decode: XXX really should move to separate stage
-        a1 = FPNumIn(None, self.width)
-        b1 = FPNumIn(None, self.width)
+        a1 = FPNumDecode(None, self.width)
+        b1 = FPNumDecode(None, self.width)
         m.submodules.sc_decode_a = a1
         m.submodules.sc_decode_b = b1
-        m.d.comb += [a1.decode(self.i.a),
-                     b1.decode(self.i.b),
+        m.d.comb += [a1.v.eq(self.i.a),
+                     b1.v.eq(self.i.b),
                      self.o.a.eq(a1),
                      self.o.b.eq(b1)
                     ]
diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index 30c3a5c4..dc2c9020 100644
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -298,7 +298,8 @@ class FPNumShift(FPNumBase):
                 self.m.eq(sm.lshift(self.m, maxslen))
                ]
 
-class FPNumIn(FPNumBase):
+
+class FPNumDecode(FPNumBase):
     """ Floating-point Number Class
 
         Contains signals for an incoming copy of the value, decoded into
@@ -312,15 +313,12 @@ class FPNumIn(FPNumBase):
     """
     def __init__(self, op, width, m_extra=True):
         FPNumBase.__init__(self, width, m_extra)
-        self.latch_in = Signal()
         self.op = op
 
     def elaborate(self, platform):
         m = FPNumBase.elaborate(self, platform)
 
-        #m.d.comb += self.latch_in.eq(self.op.ack & self.op.stb)
-        #with m.If(self.latch_in):
-        #    m.d.sync += self.decode(self.v)
+        m.d.comb += self.decode(self.v)
 
         return m
 
@@ -338,6 +336,37 @@ class FPNumIn(FPNumBase):
                 self.s.eq(v[-1]),                 # sign
                 ]
 
+class FPNumIn(FPNumBase):
+    """ Floating-point Number Class
+
+        Contains signals for an incoming copy of the value, decoded into
+        sign / exponent / mantissa.
+        Also contains encoding functions, creation and recognition of
+        zero, NaN and inf (all signed)
+
+        Four extra bits are included in the mantissa: the top bit
+        (m[-1]) is effectively a carry-overflow.  The other three are
+        guard (m[2]), round (m[1]), and sticky (m[0])
+    """
+    def __init__(self, op, width, m_extra=True):
+        FPNumBase.__init__(self, width, m_extra)
+        self.latch_in = Signal()
+        self.op = op
+
+    def decode(self, v):
+        """ decodes a latched value into sign / exponent / mantissa
+
+            bias is subtracted here, from the exponent.  exponent
+            is extended to 10 bits so that subtract 127 is done on
+            a 10-bit number
+        """
+        args = [0] * self.m_extra + [v[0:self.e_start]] # pad with extra zeros
+        #print ("decode", self.e_end)
+        return [self.m.eq(Cat(*args)), # mantissa
+                self.e.eq(v[self.e_start:self.e_end] - self.P127), # exp
+                self.s.eq(v[-1]),                 # sign
+                ]
+
     def shift_down(self, inp):
         """ shifts a mantissa down by one. exponent is increased to compensate