From: N. Engelhardt <nak@symbioticeda.com>
Date: Mon, 30 Mar 2020 11:51:12 +0000 (+0200)
Subject: Merge pull request #1778 from rswarbrick/sv-defines
X-Git-Tag: working-ls180~723
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c847e7efec5e940331a94580fad99375ce73c6f;p=yosys.git

Merge pull request #1778 from rswarbrick/sv-defines

Add support for SystemVerilog-style `define to Verilog frontend
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2c847e7efec5e940331a94580fad99375ce73c6f