From: Eric Christopher Date: Tue, 4 Dec 2001 06:30:02 +0000 (+0000) Subject: mips.h (CALL_REALLY_USED_REGISTERS): New macro. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ca2d9ee0f4845d32453142ed3466dd7116906c7;p=gcc.git mips.h (CALL_REALLY_USED_REGISTERS): New macro. 2001-12-03 Eric Christopher * config/mips/mips.h (CALL_REALLY_USED_REGISTERS): New macro. * config/mips/mips.md: Check TARGET_DEBUG_D_MODE before split patterns. From-SVN: r47590 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b9dcc87f4b9..b078b6612e9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2001-12-03 Eric Christopher + + * config/mips/mips.h (CALL_REALLY_USED_REGISTERS): New macro. + * config/mips/mips.md: Check TARGET_DEBUG_D_MODE before split + patterns. + 2001-12-03 Janis Johnson * rtl.def (PREFETCH): New rtx code. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 106026b4b71..b0415087faf 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1716,6 +1716,25 @@ do { \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } +/* Like `CALL_USED_REGISTERS' but used to overcome a historical + problem which makes CALL_USED_REGISTERS *always* include + all the FIXED_REGISTERS. Until this problem has been + resolved this macro can be used to overcome this situation. + In particular, block_propagate() requires this list + be acurate, or we can remove registers which should be live. + This macro is used in regs_invalidated_by_call. */ + + +#define CALL_REALLY_USED_REGISTERS \ +{ /* General registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \ + /* Floating-point registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + /* Others. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ +} /* Internal macros to classify a register number as to whether it's a general purpose register, a floating point register, a diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index a69440891a1..0a0fae45cd9 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -688,7 +688,7 @@ [(set (match_operand:SI 0 "register_operand" "") (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand" "")))] - "TARGET_MIPS16 && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -718,7 +718,7 @@ [(set (match_operand:SI 0 "register_operand" "") (plus:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_MIPS16 && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG @@ -1007,7 +1007,7 @@ [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_dup 0) (match_operand:DI 1 "const_int_operand" "")))] - "TARGET_MIPS16 && TARGET_64BIT && reload_completed + "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -1037,7 +1037,7 @@ [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "const_int_operand" "")))] - "TARGET_MIPS16 && TARGET_64BIT && reload_completed + "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG @@ -1222,7 +1222,7 @@ [(set (match_operand:SI 0 "register_operand" "") (minus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand" "")))] - "TARGET_MIPS16 && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -1252,7 +1252,7 @@ [(set (match_operand:SI 0 "register_operand" "") (minus:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_MIPS16 && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG @@ -1508,7 +1508,7 @@ [(set (match_operand:DI 0 "register_operand" "") (minus:DI (match_dup 0) (match_operand:DI 1 "const_int_operand" "")))] - "TARGET_MIPS16 && TARGET_64BIT && reload_completed + "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -1538,7 +1538,7 @@ [(set (match_operand:DI 0 "register_operand" "") (minus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "const_int_operand" "")))] - "TARGET_MIPS16 && TARGET_64BIT && reload_completed + "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG @@ -1824,7 +1824,9 @@ (clobber (match_scratch:SI 5 "")) (clobber (match_scratch:SI 6 "")) (clobber (match_scratch:SI 7 ""))] - "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[3]))" + "reload_completed && !TARGET_DEBUG_D_MODE + && GP_REG_P (true_regnum (operands[0])) + && GP_REG_P (true_regnum (operands[3]))" [(parallel [(set (match_dup 7) (mult:SI (match_dup 1) (match_dup 2))) (clobber (match_dup 4)) @@ -1843,7 +1845,8 @@ (clobber (match_scratch:SI 5 "")) (clobber (match_scratch:SI 6 "")) (clobber (match_scratch:SI 7 ""))] - "reload_completed && GP_REG_P (true_regnum (operands[0])) + "reload_completed && !TARGET_DEBUG_D_MODE + && GP_REG_P (true_regnum (operands[0])) && true_regnum (operands[3]) == LO_REGNUM" [(parallel [(set (match_dup 3) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) @@ -1885,7 +1888,9 @@ (clobber (match_scratch:SI 5 "")) (clobber (match_scratch:SI 6 "")) (clobber (match_scratch:SI 7 ""))] - "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[1]))" + "reload_completed && !TARGET_DEBUG_D_MODE + && GP_REG_P (true_regnum (operands[0])) + && GP_REG_P (true_regnum (operands[1]))" [(parallel [(set (match_dup 7) (mult:SI (match_dup 2) (match_dup 3))) (clobber (match_dup 4)) @@ -1904,7 +1909,8 @@ (clobber (match_scratch:SI 5 "")) (clobber (match_scratch:SI 6 "")) (clobber (match_scratch:SI 7 ""))] - "reload_completed && GP_REG_P (true_regnum (operands[0])) + "reload_completed && !TARGET_DEBUG_D_MODE + && GP_REG_P (true_regnum (operands[0])) && true_regnum (operands[1]) == LO_REGNUM" [(parallel [(set (match_dup 1) (minus:SI (match_dup 1) @@ -1926,7 +1932,9 @@ (clobber (match_scratch:SI 5 "")) (clobber (match_scratch:SI 6 "")) (clobber (match_scratch:SI 7 ""))] - "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[1]))" + "reload_completed && !TARGET_DEBUG_D_MODE + && GP_REG_P (true_regnum (operands[0])) + && GP_REG_P (true_regnum (operands[1]))" [(parallel [(set (match_dup 7) (mult:SI (match_dup 2) (match_dup 3))) (clobber (match_dup 4)) @@ -3239,7 +3247,8 @@ move\\t%0,%z4\\n\\ (define_split [(set (match_operand:DI 0 "register_operand" "") (not:DI (match_operand:DI 1 "register_operand" "")))] - "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + "reload_completed && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" @@ -3341,7 +3350,8 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DI 0 "register_operand" "") (and:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "register_operand" "")))] - "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + "reload_completed && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" @@ -3442,7 +3452,8 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DI 0 "register_operand" "") (ior:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "register_operand" "")))] - "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + "reload_completed && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" @@ -3546,7 +3557,8 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DI 0 "register_operand" "") (xor:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "register_operand" "")))] - "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + "reload_completed && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" @@ -3595,7 +3607,8 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DI 0 "register_operand" "") (and:DI (not:DI (match_operand:DI 1 "register_operand" "")) (not:DI (match_operand:DI 2 "register_operand" ""))))] - "reload_completed && !TARGET_MIPS16 && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + "reload_completed && !TARGET_MIPS16 && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" @@ -5037,7 +5050,8 @@ move\\t%0,%z4\\n\\ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" ""))] - "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + "reload_completed && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" @@ -5095,6 +5109,7 @@ move\\t%0,%z4\\n\\ (mem:DI (plus:DI (match_dup 0) (match_operand:DI 1 "const_int_operand" ""))))] "TARGET_64BIT && TARGET_MIPS16 && reload_completed + && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -5514,7 +5529,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:SI 0 "register_operand" "") (mem:SI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand" ""))))] - "TARGET_MIPS16 && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -5556,7 +5571,7 @@ move\\t%0,%z4\\n\\ (define_split [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] - "TARGET_MIPS16 && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -5578,7 +5593,7 @@ move\\t%0,%z4\\n\\ (define_split [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] - "TARGET_MIPS16 && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -6001,7 +6016,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:HI 0 "register_operand" "") (mem:HI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand" ""))))] - "TARGET_MIPS16 && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -6123,7 +6138,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:QI 0 "register_operand" "") (mem:QI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand" ""))))] - "TARGET_MIPS16 && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[0]) == REG && M16_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == CONST_INT @@ -6284,7 +6299,8 @@ move\\t%0,%z4\\n\\ (define_split [(set (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "register_operand" ""))] - "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + "reload_completed && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) @@ -6540,8 +6556,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:SI 0 "register_operand" "") (ashift:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_MIPS16 - && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16" @@ -6818,7 +6833,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DI 0 "register_operand" "") (ashift:DI (match_operand:DI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_MIPS16 && TARGET_64BIT + "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE && reload_completed && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 8 @@ -6902,8 +6917,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:SI 0 "register_operand" "") (ashiftrt:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_MIPS16 - && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16" @@ -7007,7 +7021,8 @@ move\\t%0,%z4\\n\\ (ashiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:SI 2 "small_int" ""))) (clobber (match_operand:SI 3 "register_operand" ""))] - "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER && (INTVAL (operands[2]) & 32) != 0" @@ -7023,7 +7038,8 @@ move\\t%0,%z4\\n\\ (ashiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:SI 2 "small_int" ""))) (clobber (match_operand:SI 3 "register_operand" ""))] - "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER && (INTVAL (operands[2]) & 32) != 0" @@ -7167,7 +7183,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DI 0 "register_operand" "") (ashiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_MIPS16 && TARGET_64BIT + "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE && reload_completed && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 8 @@ -7251,8 +7267,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:SI 0 "register_operand" "") (lshiftrt:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_MIPS16 - && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16" @@ -7290,7 +7305,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:SI 0 "register_operand" "") (lshiftrt:SI (match_operand:SI 1 "memory_operand" "") (match_operand:SI 2 "immediate_operand" "")))] - "TARGET_MIPS16" + "TARGET_MIPS16 && !TARGET_DEBUG_D_MODE" [(set (match_dup 0) (match_dup 1)) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] "") @@ -7552,8 +7567,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DI 0 "register_operand" "") (lshiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_MIPS16 - && reload_completed + "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16" @@ -9647,7 +9661,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" (define_split [(unspec [(match_operand 0 "register_operand" "")] 3) (clobber (match_scratch 1 ""))] - "reload_completed" + "reload_completed && !TARGET_DEBUG_D_MODE" [(const_int 0)] " {