From: Dmitry Selyutin Date: Sat, 14 May 2022 20:10:02 +0000 (+0000) Subject: ppc-opc: support grevwi and grevwi. instructions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ca46f1a329edf8787ad30367fae7b034411603d;p=binutils-gdb.git ppc-opc: support grevwi and grevwi. instructions --- diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 5e74cd547be..42d29d83a43 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -3382,6 +3382,7 @@ const struct powerpc_operand powerpc_operands[] = /* The FC field in an atomic X form instruction. */ #define FC SH #define UIM5 SH +#define XBI5 SH { 0x1f, 11, NULL, NULL, 0 }, #define RRWn SH + 1 @@ -5875,6 +5876,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"grevw.", XBM5(5,182,1), XBM5_MASK, DRAFT, PPCVLE, {RT, RA, RB}}, {"grevi", XBM6(5,214,0), XBM6_MASK, DRAFT, PPCVLE, {RT, RA, XBI6}}, {"grevi.", XBM6(5,214,1), XBM6_MASK, DRAFT, PPCVLE, {RT, RA, XBI6}}, +{"grevwi", XBM5(5,246,0), XBM5_MASK, DRAFT, PPCVLE, {RT, RA, XBI5}}, +{"grevwi.", XBM5(5,246,1), XBM5_MASK, DRAFT, PPCVLE, {RT, RA, XBI5}}, {"lxvp", DQXP(6,0), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}}, {"stxvp", DQXP(6,1), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}},