From: Julia Koval Date: Mon, 16 Apr 2018 05:59:52 +0000 (+0200) Subject: Add sse_unaligned_load_optimal and sse_unaligned_store_optimal to Skylake. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cb0369c9e62f450a3dd9b227f0ae29659639a56;p=gcc.git Add sse_unaligned_load_optimal and sse_unaligned_store_optimal to Skylake. gcc/ PR target/84413 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Add m_SKYLAKE_AVX512 From-SVN: r259395 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9b7f84582a4..a04b68f7524 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-04-16 Julia Koval + + PR target/84413 + * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, + X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Add m_SKYLAKE_AVX512 + 2018-04-14 Segher Boessenkool PR target/85293 diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 9843ed806f6..5649fdcf416 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -336,13 +336,14 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill", of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal", m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM - | m_INTEL | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER1 | m_GENERIC) + | m_INTEL | m_SKYLAKE_AVX512 | m_AMDFAM10 | m_BDVER | m_BTVER + | m_ZNVER1 | m_GENERIC) /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal", m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM - | m_INTEL | m_BDVER | m_ZNVER1 | m_GENERIC) + | m_INTEL | m_SKYLAKE_AVX512 | m_BDVER | m_ZNVER1 | m_GENERIC) /* Use packed single precision instructions where posisble. I.e. movups instead of movupd. */