From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 7 Oct 2019 22:03:44 +0000 (-0700)
Subject: Use "abc9_period" attribute for delay target
X-Git-Tag: working-ls180~881^2^2~171
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cb2116b4c4d94c08be1fa087dca217eb6c0f7b9;p=yosys.git

Use "abc9_period" attribute for delay target
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2ceaacf87..34cdd3c3e 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -852,8 +852,17 @@ struct Abc9Pass : public Pass {
 		log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
 		log("ABC on logic snippets extracted from your design. You will not get any useful\n");
 		log("output when passing an ABC script that writes a file. Instead write your full\n");
-		log("design as BLIF file with write_blif and then load that into ABC externally if\n");
-		log("you want to use ABC to convert your design into another format.\n");
+		log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n");
+		log("if you want to use ABC to convert your design into another format.\n");
+		log("\n");
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("Delay targets can also be specified on a per clock basis by attaching a\n");
+		log("'(* abc9_period = <int> *)' attribute onto clock wires (specifically, onto wires\n");
+		log("that appear inside any special '$abc9_clock' wires inserted by abc9_map.v). This\n");
+		log("can be achieved by modifying the source directly, or through a `setattr`\n");
+		log("invocation. Since such attributes cannot yet be propagated through a\n");
+		log("hierarchical design (whether or not it has been uniquified) it is recommended\n");
+		log("that the design be flattened when using this feature.\n");
 		log("\n");
 		log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
 		log("\n");
@@ -1222,10 +1231,22 @@ struct Abc9Pass : public Pass {
 			design->selection_stack.emplace_back(false);
 			design->selected_active_module = module->name.str();
 			for (auto &it : assigned_cells) {
+				std::string target = delay_target;
+				if (target.empty()) {
+					for (auto b : assign_map(it.first))
+						if (b.wire) {
+							auto jt = b.wire->attributes.find("\\abc9_period");
+							if (jt != b.wire->attributes.end()) {
+								target = stringf("-D %d", jt->second.as_int());
+								log("Target period = %s ps for clock domain %s\n", target.c_str(), log_signal(it.first));
+								break;
+							}
+						}
+				}
 				RTLIL::Selection& sel = design->selection_stack.back();
 				sel.selected_members[module->name] = std::move(it.second);
 				abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, false, "$",
-						keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
+						keepff, target, lutin_shared, fast_mode, show_tempdir,
 						box_file, lut_file, wire_delay, box_lookup, nomfs);
 				assign_map.set(module);
 			}