From: lkcl Date: Sat, 7 May 2022 11:39:53 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2335 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cb4663a149c4349d7148920cb300c8a3cbd16b0;p=libreriscv.git --- diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 1c63c2c55..e92228cb1 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -369,9 +369,12 @@ to be corrected. One deliberate decision in SVP64 involves Predication. Typical Vector ISAs have quite comprehensive arithmetic and logical operations on -Predicate Masks, and if CR Fields were the only predicates in SVP64 +Predicate Masks, and it turns out, unsurprisingly, that the Scalar Integer +side of Power ISA already has most of them. +If CR Fields were the only predicates in SVP64 it would put pressure on to start adding the exact same arithmetic and logical -operations that already exist in the Integer opcodes. +operations that already exist in the Integer opcodes, which is less +than desirable. Instead of taking that route the decision was made to allow *both* Integer *and* CR Fields to be Predicate Masks, and to create Draft instructions that provide better transfer capability between CR Fields