From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 25 Sep 2017 23:52:59 +0000 (+0200)
Subject: Fix ignoring of simulation timings so that invalid module parameters cause syntax... 
X-Git-Tag: yosys-0.8~316
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cc09161ffd774430293dfd18e307e75bea73c5e;p=yosys.git

Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
---

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 885332b76..07d85bed8 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -389,10 +389,6 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 \\[\r\n]		/* ignore continuation sequence */
 "//"[^\r\n]*		/* ignore one-line comments */
 
-"#"\ *[0-9][0-9_]*			/* ignore simulation timings */
-"#"\ *[0-9][0-9_]*\.[0-9][0-9_]*	/* ignore simulation timings */
-"#"\ *[$a-zA-Z_\.][$a-zA-Z_0-9\.]*	/* ignore simulation timings */
-
 . { return *yytext; }
 
 %%
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index c5ff3d402..9fa2a1a2f 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -355,6 +355,8 @@ package_body_stmt:
 	localparam_decl;
 
 non_opt_delay:
+	'#' TOK_ID { delete $2; } |
+	'#' TOK_CONSTVAL { delete $2; } |
 	'#' '(' expr ')' { delete $3; } |
 	'#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };