From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 1 May 2012 00:08:31 +0000 (-0500)
Subject: tb/asmicon_wb: better access pattern
X-Git-Tag: 24jan2021_ls180~3196
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ccdade88eef189c899a814d64b493cab2b138b2;p=litex.git

tb/asmicon_wb: better access pattern
---

diff --git a/tb/asmicon/asmicon_wb.py b/tb/asmicon/asmicon_wb.py
index bdc1d7da..28f6dc28 100644
--- a/tb/asmicon/asmicon_wb.py
+++ b/tb/asmicon/asmicon_wb.py
@@ -10,9 +10,18 @@ from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 l2_size = 8192 # in bytes
 
 def my_generator():
-	for x in range(100):
+	for x in range(20):
+		t = TWrite(x, x)
+		yield t
+		print(str(t) + " delay=" + str(t.latency))
+	for x in range(20):
 		t = TRead(x)
 		yield t
+		print(str(t) + " delay=" + str(t.latency))
+	for x in range(20):
+		t = TRead(x+l2_size//4)
+		yield t
+		print(str(t) + " delay=" + str(t.latency))
 
 def main():
 	controller = ASMIcon(sdram_phy, sdram_geom, sdram_timing)