From: Luke Kenneth Casson Leighton Date: Sat, 23 Jul 2022 14:59:31 +0000 (+0100) Subject: add bold to exec summary, link to bigint analysis X-Git-Tag: opf_rfc_ls005_v1~1068 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cd85fc482466eaf8eb82dba3ae919d6cae17fd9;p=libreriscv.git add bold to exec summary, link to bigint analysis --- diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index 00f78b6cd..97db1faf5 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -10,7 +10,7 @@ |Aurora SX (21)|~200 (22) |Scalable (23) |yes |yes |no |yes |no |no |no |no |no |no | * (1): plus EXT001 24-bit prefixing. See [[sv/svp64]] -* (2): A 2-Dimensional Scalable Vector ISA with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]] +* (2): A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]] * (3): on specific operations. See [[opcode_regs_deduped]] for full list * (4): SVP64 provides a Vector concept on top of the **Scalar** GPR, FPR and CR Fields, extended to 128 entries. * (5): SVP64 Vectorises Scalar instructions. It is up to the **implementor** to choose (**optionally**) whether to apply SVP64 to e.g. VSX Quad-Precision (128-bit) instructions, to create 128-bit Vector operations.