From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 12 Jul 2018 02:19:56 +0000 (+0100)
Subject: add slids
X-Git-Tag: convert-csv-opcode-to-binary~5058
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cdc7406ddae52e63b411693dacba233bc13405c;p=libreriscv.git

add slids
---

diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index 47afd4dc8..a6edf26d5 100644
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -27,11 +27,14 @@
 \frame{\frametitle{Credits and Acknowledgements}
 
  \begin{itemize}
-   \item The Designers of RISC-V\vspace{15pt}
-   \item The Shakti Group\vspace{15pt}
-   \item Prof. G S Madhusudan\vspace{15pt}
-   \item Neel Gala\vspace{15pt}
-   \item Rishabh Jain\vspace{15pt}
+   \item The Designers of RISC-V\vspace{8pt}
+   \item The RISC-V Foundation\vspace{8pt}
+   \item The Shakti Group, and IIT Madras RISE Group\vspace{8pt}
+   \item Prof. G S Madhusudan\vspace{8pt}
+   \item Neel Gala\vspace{8pt}
+   \item Rishabh Jain\vspace{8pt}
+   \item Members of the RISC-V Open Groups (SW/HW/ISA)\vspace{8pt}
+   \item Libre and Open Software and Hardware Communities
   \end{itemize}
 }
 
@@ -220,7 +223,7 @@
  \begin{itemize}
    \item DDR3/4 PHYs are analog and very high speed.
 		   Impedance training.  Extreme timing tolerances on parallel buses.\\
-		   No surprise they cost USD \$1m and above.
+		   No surprise proprietary cost is USD \$1m and above.
    \item Symbiotic EDA will do (Libre) PHY layout for USD \$300k,
 	     time to completion for chosen geometry: 8-12 months.
   \end{itemize}