From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 11:41:44 +0000 (+0100)
Subject: attempt to make carry-in and overflow-enable optional on ALU
X-Git-Tag: div_pipeline~637^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cdec1db7eab5c9831662fcca4c2cae8da43f969;p=soc.git

attempt to make carry-in and overflow-enable optional on ALU
---

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 4e90b8db..662159a3 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -70,8 +70,8 @@ def regspec_decode(e, regfile, name):
         CA = 1<<XERRegs.CA
         OV = 1<<XERRegs.OV
         if name == 'xer_so':
-            return Const(1), SO, SO # TODO
             #return e.oe.oe & e.oe.oe_ok, SO, SO
+            return Const(1), SO, SO # TODO
         if name == 'xer_ov':
             return Const(1), OV, OV # TODO
             return e.oe.oe & e.oe.oe_ok, OV, OV
diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 8517dc74..5c57679e 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -53,12 +53,18 @@ def set_alu_inputs(alu, dec2, sim):
 
 
 def set_extra_alu_inputs(alu, dec2, sim):
-    carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
-    carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
-    yield alu.p.data_i.xer_ca[0].eq(carry)
-    yield alu.p.data_i.xer_ca[1].eq(carry32)
-    so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
-    yield alu.p.data_i.xer_so.eq(so)
+    cry_in = yield dec2.e.input_carry
+    if cry_in:
+        carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
+        carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+        yield alu.p.data_i.xer_ca[0].eq(carry)
+        yield alu.p.data_i.xer_ca[1].eq(carry32)
+        print ("extra inputs: CA/32", carry, carry32)
+    oe = yield dec2.e.oe.data & dec2.e.oe.ok
+    if oe:
+        so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+        print ("extra inputs: so", so)
+        yield alu.p.data_i.xer_so.eq(so)
 
 
 # This test bench is a bit different than is usual. Initially when I
diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 12475250..87ba1bc7 100644
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -32,13 +32,17 @@ class ALUTestRunner(TestRunner):
             res['rb'] = sim.gpr(data2).value
 
         # XER.ca
-        carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
-        carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
-        res['xer_ca'] = carry | (carry32<<1)
+        cry_in = yield dec2.e.input_carry
+        if True: #cry_in:
+            carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
+            carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+            res['xer_ca'] = carry | (carry32<<1)
 
         # XER.so
-        so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
-        res['xer_so'] = so
+        oe = yield dec2.e.oe.data & dec2.e.oe.ok
+        if True: #oe:
+            so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+            res['xer_so'] = so
 
         return res