From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 May 2020 13:59:30 +0000 (+0100)
Subject: missing sticky-overflow pass-through from middle stage
X-Git-Tag: div_pipeline~1318
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ce8648ea81d401318d595b2adf9b48d18acc93e;p=soc.git

missing sticky-overflow pass-through from middle stage
---

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index e801c966..07fb0180 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -39,7 +39,9 @@ class ALUMainStage(PipeModBase):
             with m.Case(InternalOp.OP_XOR):
                 comb += self.o.o.eq(self.i.a ^ self.i.b)
 
+        ###### sticky overflow and context, both pass-through #####
 
+        comb += so.eq(self.i.so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m