From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Nov 2018 02:34:51 +0000 (+0000)
Subject: start on csr op valid
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cfab105ed1b43c539bb44f8ac62b1f2fb014ed9;p=rv32.git

start on csr op valid
---

diff --git a/cpu.py b/cpu.py
index b79615c..8baa0be 100644
--- a/cpu.py
+++ b/cpu.py
@@ -329,40 +329,70 @@ class CPU(Module):
         return s
 
     """
-    task handle_trap;
+    function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
     begin
-        mstatus_mpie = mstatus_mie;
-        mstatus_mie = 0;
-        mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
-        if(fetch_action == `fetch_action_ack_trap) begin
-            mcause = `cause_instruction_access_fault;
-        end
-        else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
-            mcause = `cause_illegal_instruction;
-        end
-        else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
-            mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
-        end
-        else if((decode_action & `decode_action_load) != 0) begin
-            if(load_store_misaligned)
-                mcause = `cause_load_address_misaligned;
-            else
-                mcause = `cause_load_access_fault;
-        end
-        else if((decode_action & `decode_action_store) != 0) begin
-            if(load_store_misaligned)
-                mcause = `cause_store_amo_address_misaligned;
-            else
-                mcause = `cause_store_amo_access_fault;
-        end
-        else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
-            mcause = `cause_instruction_address_misaligned;
-        end
-        else begin
-            mcause = `cause_illegal_instruction;
-        end
+        case(csr_number)
+        `csr_ustatus,
+        `csr_fflags,
+        `csr_frm,
+        `csr_fcsr,
+        `csr_uie,
+        `csr_utvec,
+        `csr_uscratch,
+        `csr_uepc,
+        `csr_ucause,
+        `csr_utval,
+        `csr_uip,
+        `csr_sstatus,
+        `csr_sedeleg,
+        `csr_sideleg,
+        `csr_sie,
+        `csr_stvec,
+        `csr_scounteren,
+        `csr_sscratch,
+        `csr_sepc,
+        `csr_scause,
+        `csr_stval,
+        `csr_sip,
+        `csr_satp,
+        `csr_medeleg,
+        `csr_mideleg,
+        `csr_dcsr,
+        `csr_dpc,
+        `csr_dscratch:
+            get_csr_op_is_valid = 0;
+        `csr_cycle,
+        `csr_time,
+        `csr_instret,
+        `csr_cycleh,
+        `csr_timeh,
+        `csr_instreth,
+        `csr_mvendorid,
+        `csr_marchid,
+        `csr_mimpid,
+        `csr_mhartid:
+            get_csr_op_is_valid = ~csr_writes;
+        `csr_misa,
+        `csr_mstatus,
+        `csr_mie,
+        `csr_mtvec,
+        `csr_mscratch,
+        `csr_mepc,
+        `csr_mcause,
+        `csr_mip:
+            get_csr_op_is_valid = 1;
+        `csr_mcounteren,
+        `csr_mtval,
+        `csr_mcycle,
+        `csr_minstret,
+        `csr_mcycleh,
+        `csr_minstreth:
+            // TODO: CSRs not implemented yet
+            get_csr_op_is_valid = 0;
+        endcase
     end
-    endtask
+    endfunction
+
     """
 
     def __init__(self):
@@ -639,11 +669,6 @@ if __name__ == "__main__":
 
 """
 
-    wire [11:0] csr_number = decoder_immediate;
-    wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
-    wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
-    wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
-
     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
     begin
         case(csr_number)