From: Gabe Black <gabe.black@gmail.com>
Date: Sun, 1 Nov 2020 08:53:03 +0000 (-0700)
Subject: arch,cpu: Enforce using accessors to get at src/destRegIdx.
X-Git-Tag: develop-gem5-snapshot~508
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cfc24b8dc27acc0ef2ac421b79f839c0354fefd;p=gem5.git

arch,cpu: Enforce using accessors to get at src/destRegIdx.

There were accessors for reading these indexes, but they were not
consistently used. This change makes them private to StaticInst, and
changes places that were accessing them directly to instead use the
accessors. New accessors are added for code generated by the ISA parser
and some ARM code to set the indexes without accessing them directly.

By forcing these values to be behind accessors, it will be much simpler
to change how those values are stored and retrieved.

Change-Id: Icca80023d7f89e29504fac6b194881f88aedeec2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36875
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index 3629d34ae..d32e8c9f8 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -123,7 +123,7 @@ Tstart64::Tstart64(ExtMachInst machInst, IntRegIndex _dest)
     _numVecElemDestRegs = 0;
     _numIntDestRegs = 0;
     _numCCDestRegs = 0;
-    _destRegIdx[_numDestRegs++] = RegId(IntRegClass, dest);
+    setDestRegIdx(_numDestRegs++, RegId(IntRegClass, dest));
     _numIntDestRegs++;
     flags[IsHtmStart] = true;
     flags[IsInteger] = true;
@@ -151,7 +151,7 @@ Ttest64::Ttest64(ExtMachInst machInst, IntRegIndex _dest)
     _numVecElemDestRegs = 0;
     _numIntDestRegs = 0;
     _numCCDestRegs = 0;
-    _destRegIdx[_numDestRegs++] = RegId(IntRegClass, dest);
+    setDestRegIdx(_numDestRegs++, RegId(IntRegClass, dest));
     _numIntDestRegs++;
     flags[IsInteger] = true;
     flags[IsMicroop] = true;
diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa
index 7210472d3..cde0ce0ff 100644
--- a/src/arch/arm/isa/templates/basic.isa
+++ b/src/arch/arm/isa/templates/basic.isa
@@ -60,7 +60,7 @@ def template BasicConstructor {{
                 %(constructor)s;
                 if (!(condCode == COND_AL || condCode == COND_UC)) {
                     for (int x = 0; x < _numDestRegs; x++) {
-                        _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                        setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
                     }
                 }
         }
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index c765cf7c3..cccd67f07 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -61,7 +61,7 @@ def template BranchImmCondConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
             flags[IsCondControl] = true;
         } else {
@@ -91,7 +91,7 @@ def template BranchRegCondConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
             flags[IsCondControl] = true;
         } else {
@@ -125,7 +125,7 @@ def template BranchRegRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
             flags[IsCondControl] = true;
         } else {
diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa
index 13ae6dd16..0eb918e0a 100644
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -69,7 +69,7 @@ def template MicroMemConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -103,7 +103,7 @@ def template MicroMemPairConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -128,7 +128,7 @@ def template MicroNeonMemDeclare {{
             %(constructor)s;
             if (!(condCode == COND_AL || condCode == COND_UC)) {
                 for (int x = 0; x < _numDestRegs; x++) {
-                    _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                    setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
                 }
             }
         }
@@ -170,7 +170,7 @@ def template MicroSetPCCPSRConstructor {{
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             flags[IsCondControl] = true;
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         } else {
             flags[IsUncondControl] = true;
@@ -219,7 +219,7 @@ def template MicroNeonMixDeclare {{
             %(constructor)s;
             if (!(condCode == COND_AL || condCode == COND_UC)) {
                 for (int x = 0; x < _numDestRegs; x++) {
-                    _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                    setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
                 }
             }
         }
@@ -272,7 +272,7 @@ def template MicroNeonMixLaneDeclare {{
             %(constructor)s;
             if (!(condCode == COND_AL || condCode == COND_UC)) {
                 for (int x = 0; x < _numDestRegs; x++) {
-                    _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                    setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
                 }
             }
         }
@@ -305,7 +305,7 @@ def template MicroIntMovConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -338,7 +338,7 @@ def template MicroIntImmConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -399,7 +399,7 @@ def template MicroIntRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -434,7 +434,7 @@ def template MacroMemConstructor {{
     %(constructor)s;
     if (!(condCode == COND_AL || condCode == COND_UC)) {
         for (int x = 0; x < _numDestRegs; x++) {
-            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+            setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
         }
     }
 }
@@ -548,7 +548,7 @@ def template VMemMultConstructor {{
     %(constructor)s;
     if (!(condCode == COND_AL || condCode == COND_UC)) {
         for (int x = 0; x < _numDestRegs; x++) {
-            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+            setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
         }
     }
 }
@@ -575,7 +575,7 @@ def template VMemSingleConstructor {{
     %(constructor)s;
     if (!(condCode == COND_AL || condCode == COND_UC)) {
         for (int x = 0; x < _numDestRegs; x++) {
-            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+            setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
         }
     }
 }
@@ -605,7 +605,7 @@ def template MacroVFPMemConstructor {{
     %(constructor)s;
     if (!(condCode == COND_AL || condCode == COND_UC)) {
         for (int x = 0; x < _numDestRegs; x++) {
-            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+            setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
         }
     }
 }
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index b056f48e8..c0356c9c9 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -852,7 +852,7 @@ def template RfeConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -882,7 +882,7 @@ def template SrsConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -906,7 +906,7 @@ def template SwapConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -923,7 +923,7 @@ def template LoadStoreDImmConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -950,7 +950,7 @@ def template StoreExDImmConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -975,7 +975,7 @@ def template LoadStoreImmConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -1001,7 +1001,7 @@ def template StoreExImmConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -1030,7 +1030,7 @@ def template StoreDRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -1058,7 +1058,7 @@ def template StoreRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -1087,7 +1087,7 @@ def template LoadDRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -1130,7 +1130,7 @@ def template LoadRegConstructor {{
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             conditional = true;
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
@@ -1196,7 +1196,7 @@ def template LoadImmConstructor {{
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             conditional = true;
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 #if %(use_uops)d
diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa
index 3b90f8c3f..98d064554 100644
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -875,11 +875,11 @@ def template AmoPairOpConstructor {{
         uint32_t r2 = RegId(IntRegClass, result).index() + 1 ;
 
         d2_src = _numSrcRegs ;
-        _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, d2);
+        setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass, d2));
         r2_src = _numSrcRegs ;
-        _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, r2);
+        setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass, r2));
         r2_dst = _numDestRegs ;
-        _destRegIdx[_numDestRegs++] = RegId(IntRegClass, r2);
+        setDestRegIdx(_numDestRegs++, RegId(IntRegClass, r2));
         flags[IsStore] = false;
         flags[IsLoad] = false;
     }
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 51d833700..e31146593 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -54,7 +54,7 @@ def template MrsConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -86,7 +86,7 @@ def template MrsBankedRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -117,7 +117,7 @@ def template MsrBankedRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -143,7 +143,7 @@ def template MsrRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -169,7 +169,7 @@ def template MsrImmConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -199,7 +199,7 @@ def template MrrcOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -229,7 +229,7 @@ def template McrrOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -253,7 +253,7 @@ def template ImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -278,7 +278,7 @@ def template RegImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -304,7 +304,7 @@ def template RegRegOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -335,7 +335,7 @@ def template RegRegRegImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -366,7 +366,7 @@ def template RegRegRegRegOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -395,7 +395,7 @@ def template RegRegRegOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -425,7 +425,7 @@ def template RegRegImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -455,7 +455,7 @@ def template MiscRegRegImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -485,7 +485,7 @@ def template RegMiscRegImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -514,7 +514,7 @@ def template RegImmImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -545,7 +545,7 @@ def template RegRegImmImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -574,7 +574,7 @@ def template RegImmRegOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -606,7 +606,7 @@ def template RegImmRegShiftOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa
index 03f0b71de..8ecef6a2f 100644
--- a/src/arch/arm/isa/templates/mult.isa
+++ b/src/arch/arm/isa/templates/mult.isa
@@ -57,7 +57,7 @@ def template Mult3Constructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -87,7 +87,7 @@ def template Mult4Constructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa
index 39e6d2222..5191daa2f 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -64,7 +64,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -90,7 +90,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -115,7 +115,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -138,7 +138,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 9b08fc3d3..3c770e93b 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -71,7 +71,7 @@ def template DataImmConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 
@@ -111,7 +111,7 @@ def template DataRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 
@@ -156,7 +156,7 @@ def template DataRegRegConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
diff --git a/src/arch/arm/isa/templates/semihost.isa b/src/arch/arm/isa/templates/semihost.isa
index c60db1752..7ec4e19a1 100644
--- a/src/arch/arm/isa/templates/semihost.isa
+++ b/src/arch/arm/isa/templates/semihost.isa
@@ -54,7 +54,7 @@ def template SemihostConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
 
diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index 7d59908c2..8913afde7 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -419,8 +419,11 @@ def template SveIndexedMemVIMicroopDeclare {{
                 // The first micro-op is responsible for pinning the
                 // destination and the fault status registers
                 assert(_numDestRegs == 2);
-               _destRegIdx[0].setNumPinnedWrites(numElems - 1);
-               _destRegIdx[1].setNumPinnedWrites(numElems - 1);
+                for (int i = 0; i < _numDestRegs; i++) {
+                    auto dr = destRegIdx(i);
+                    dr.setNumPinnedWrites(numElems - 1);
+                    setDestRegIdx(i, dr);
+                }
             }
         }
 
@@ -500,8 +503,11 @@ def template SveIndexedMemSVMicroopDeclare {{
                 // The first micro-op is responsible for pinning the
                 // destination and the fault status registers
                 assert(_numDestRegs == 2);
-               _destRegIdx[0].setNumPinnedWrites(numElems - 1);
-               _destRegIdx[1].setNumPinnedWrites(numElems - 1);
+                for (int i = 0; i < _numDestRegs; i++) {
+                    auto dr = destRegIdx(i);
+                    dr.setNumPinnedWrites(numElems - 1);
+                    setDestRegIdx(i, dr);
+                }
             }
         }
 
diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index b11715f43..5481350cb 100644
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -117,7 +117,7 @@ def template FpRegRegOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -143,7 +143,7 @@ def template FpRegImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -173,7 +173,7 @@ def template FpRegRegImmOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
@@ -203,7 +203,7 @@ def template FpRegRegRegOpConstructor {{
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+                setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
             }
         }
     }
diff --git a/src/arch/isa_parser/operand_types.py b/src/arch/isa_parser/operand_types.py
index cd341d038..6c3549f30 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -44,8 +44,8 @@ class Operand(object):
     derived classes encapsulates the traits of a particular operand
     type (e.g., "32-bit integer register").'''
 
-    src_reg_constructor = '\n\t_srcRegIdx[_numSrcRegs++] = RegId(%s, %s);'
-    dst_reg_constructor = '\n\t_destRegIdx[_numDestRegs++] = RegId(%s, %s);'
+    src_reg_constructor = '\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s));'
+    dst_reg_constructor = '\n\tsetDestRegIdx(_numDestRegs++, RegId(%s, %s));'
 
     def buildReadCode(self, func = None):
         subst_dict = {"name": self.base_name,
@@ -473,11 +473,11 @@ class VecElemOperand(Operand):
         numAccessNeeded = 1
 
         if self.is_src:
-            c_src = ('\n\t_srcRegIdx[_numSrcRegs++] = RegId(%s, %s, %s);' %
+            c_src = ('\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s, %s));' %
                     (self.reg_class, self.reg_spec, self.elem_spec))
 
         if self.is_dest:
-            c_dest = ('\n\t_destRegIdx[_numDestRegs++] = RegId(%s, %s, %s);' %
+            c_dest = ('\n\tsetDestRegIdx(_numDestRegs++, RegId(%s, %s, %s));' %
                     (self.reg_class, self.reg_spec, self.elem_spec))
             c_dest += '\n\t_numVecElemDestRegs++;'
         return c_src + c_dest
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 0d514671a..cdd950c69 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -98,17 +98,17 @@ output decoder {{
         // class?
         if (strcmp(mnemonic, "syscall") != 0) {
             if(_numDestRegs > 0){
-                printReg(ss, _destRegIdx[0]);
+                printReg(ss, destRegIdx(0));
             }
 
             if(_numSrcRegs > 0) {
                 ss << ", ";
-                printReg(ss, _srcRegIdx[0]);
+                printReg(ss, srcRegIdx(0));
             }
 
             if(_numSrcRegs > 1) {
                 ss << ", ";
-                printReg(ss, _srcRegIdx[1]);
+                printReg(ss, srcRegIdx(1));
             }
         }
 
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 7c2b27cc1..42a0dea38 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -182,12 +182,12 @@ output decoder {{
         // branches) or a destination (the link reg for
         // unconditional branches)
         if (_numSrcRegs == 1) {
-            printReg(ss, _srcRegIdx[0]);
+            printReg(ss, srcRegIdx(0));
             ss << ", ";
         } else if(_numSrcRegs == 2) {
-            printReg(ss, _srcRegIdx[0]);
+            printReg(ss, srcRegIdx(0));
             ss << ", ";
-            printReg(ss, _srcRegIdx[1]);
+            printReg(ss, srcRegIdx(1));
             ss << ", ";
         }
 
@@ -219,11 +219,11 @@ output decoder {{
             else
                 ccprintf(ss, "0x%x", disp);
         } else if (_numSrcRegs == 1) {
-             printReg(ss, _srcRegIdx[0]);
+             printReg(ss, srcRegIdx(0));
         } else if(_numSrcRegs == 2) {
-            printReg(ss, _srcRegIdx[0]);
+            printReg(ss, srcRegIdx(0));
             ss << ", ";
-            printReg(ss, _srcRegIdx[1]);
+            printReg(ss, srcRegIdx(1));
         }
 
         return ss.str();
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 5d8f10755..368aa5589 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -66,12 +66,12 @@ output decoder {{
 
         if (_numSrcRegs > 0) {
             ss << ", ";
-            printReg(ss, _srcRegIdx[0]);
+            printReg(ss, srcRegIdx(0));
         }
 
         if (_numSrcRegs > 1) {
             ss << ", ";
-            printReg(ss, _srcRegIdx[1]);
+            printReg(ss, srcRegIdx(1));
         }
 
         return ss.str();
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index c48ad1169..f47e72891 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -187,7 +187,7 @@ output decoder {{
         // just print the first dest... if there's a second one,
         // it's generally implicit
         if (_numDestRegs > 0) {
-            printReg(ss, _destRegIdx[0]);
+            printReg(ss, destRegIdx(0));
             ss << ", ";
         }
 
@@ -195,12 +195,12 @@ output decoder {{
         // a third one, it's a read-modify-write dest (Rc),
         // e.g. for CMOVxx
         if (_numSrcRegs > 0) {
-            printReg(ss, _srcRegIdx[0]);
+            printReg(ss, srcRegIdx(0));
         }
 
         if (_numSrcRegs > 1) {
             ss << ", ";
-            printReg(ss, _srcRegIdx[1]);
+            printReg(ss, srcRegIdx(1));
         }
 
         return ss.str();
@@ -216,12 +216,12 @@ output decoder {{
 
         // Destination Registers are implicit for HI/LO ops
         if (_numSrcRegs > 0) {
-            printReg(ss, _srcRegIdx[0]);
+            printReg(ss, srcRegIdx(0));
         }
 
         if (_numSrcRegs > 1) {
             ss << ", ";
-            printReg(ss, _srcRegIdx[1]);
+            printReg(ss, srcRegIdx(1));
         }
 
         return ss.str();
@@ -235,10 +235,10 @@ output decoder {{
 
         ccprintf(ss, "%-10s ", mnemonic);
 
-        if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
-            printReg(ss, _destRegIdx[0]);
-        } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
-            printReg(ss, _srcRegIdx[0]);
+        if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+            printReg(ss, destRegIdx(0));
+        } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+            printReg(ss, srcRegIdx(0));
         }
 
         return ss.str();
@@ -252,10 +252,10 @@ output decoder {{
 
         ccprintf(ss, "%-10s ", mnemonic);
 
-        if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
-            printReg(ss, _destRegIdx[0]);
-        } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
-            printReg(ss, _srcRegIdx[0]);
+        if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+            printReg(ss, destRegIdx(0));
+        } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+            printReg(ss, srcRegIdx(0));
         }
 
         return ss.str();
@@ -269,10 +269,10 @@ output decoder {{
 
         ccprintf(ss, "%-10s ", mnemonic);
 
-        if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
-            printReg(ss, _destRegIdx[0]);
-        } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
-            printReg(ss, _srcRegIdx[0]);
+        if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+            printReg(ss, destRegIdx(0));
+        } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+            printReg(ss, srcRegIdx(0));
         }
 
         return ss.str();
@@ -287,13 +287,13 @@ output decoder {{
         ccprintf(ss, "%-10s ", mnemonic);
 
         if (_numDestRegs > 0) {
-            printReg(ss, _destRegIdx[0]);
+            printReg(ss, destRegIdx(0));
         }
 
         ss << ", ";
 
         if (_numSrcRegs > 0) {
-            printReg(ss, _srcRegIdx[0]);
+            printReg(ss, srcRegIdx(0));
             ss << ", ";
         }
 
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 3511b6b3c..72e4412a8 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -155,7 +155,7 @@ BranchNonPCRelCond::generateDisassembly(
 PowerISA::PCState
 BranchRegCond::branchTarget(ThreadContext *tc) const
 {
-    uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index());
+    uint32_t regVal = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
     return regVal & 0xfffffffc;
 }
 
diff --git a/src/arch/power/insts/floating.cc b/src/arch/power/insts/floating.cc
index 8bdaf1d21..5ccaac9df 100644
--- a/src/arch/power/insts/floating.cc
+++ b/src/arch/power/insts/floating.cc
@@ -39,7 +39,7 @@ FloatOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
     // Print the first destination only
     if (_numDestRegs > 0) {
-        printReg(ss, _destRegIdx[0]);
+        printReg(ss, destRegIdx(0));
     }
 
     // Print the (possibly) two source registers
@@ -47,10 +47,10 @@ FloatOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
         if (_numDestRegs > 0) {
             ss << ", ";
         }
-        printReg(ss, _srcRegIdx[0]);
+        printReg(ss, srcRegIdx(0));
         if (_numSrcRegs > 1) {
           ss << ", ";
-          printReg(ss, _srcRegIdx[1]);
+          printReg(ss, srcRegIdx(1));
         }
     }
 
diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index 84362dea5..8522153e2 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -43,7 +43,7 @@ IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
     string myMnemonic(mnemonic);
 
     // Special cases
-    if (!myMnemonic.compare("or") && _srcRegIdx[0] == _srcRegIdx[1]) {
+    if (!myMnemonic.compare("or") && srcRegIdx(0) == srcRegIdx(1)) {
         myMnemonic = "mr";
         printSecondSrc = false;
     } else if (!myMnemonic.compare("mtlr") || !myMnemonic.compare("cmpi")) {
@@ -59,7 +59,7 @@ IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
     // Print the first destination only
     if (_numDestRegs > 0 && printDest) {
-        printReg(ss, _destRegIdx[0]);
+        printReg(ss, destRegIdx(0));
     }
 
     // Print the (possibly) two source registers
@@ -67,10 +67,10 @@ IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
         if (_numDestRegs > 0 && printDest) {
             ss << ", ";
         }
-        printReg(ss, _srcRegIdx[0]);
+        printReg(ss, srcRegIdx(0));
         if (_numSrcRegs > 1 && printSecondSrc) {
           ss << ", ";
-          printReg(ss, _srcRegIdx[1]);
+          printReg(ss, srcRegIdx(1));
         }
     }
 
@@ -96,7 +96,7 @@ IntImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
     // Print the first destination only
     if (_numDestRegs > 0) {
-        printReg(ss, _destRegIdx[0]);
+        printReg(ss, destRegIdx(0));
     }
 
     // Print the source register
@@ -104,7 +104,7 @@ IntImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
         if (_numDestRegs > 0) {
             ss << ", ";
         }
-        printReg(ss, _srcRegIdx[0]);
+        printReg(ss, srcRegIdx(0));
     }
 
     // Print the immediate value last
@@ -124,7 +124,7 @@ IntShiftOp::generateDisassembly(
 
     // Print the first destination only
     if (_numDestRegs > 0) {
-        printReg(ss, _destRegIdx[0]);
+        printReg(ss, destRegIdx(0));
     }
 
     // Print the first source register
@@ -132,7 +132,7 @@ IntShiftOp::generateDisassembly(
         if (_numDestRegs > 0) {
             ss << ", ";
         }
-        printReg(ss, _srcRegIdx[0]);
+        printReg(ss, srcRegIdx(0));
     }
 
     // Print the shift
@@ -152,7 +152,7 @@ IntRotateOp::generateDisassembly(
 
     // Print the first destination only
     if (_numDestRegs > 0) {
-        printReg(ss, _destRegIdx[0]);
+        printReg(ss, destRegIdx(0));
     }
 
     // Print the first source register
@@ -160,7 +160,7 @@ IntRotateOp::generateDisassembly(
         if (_numDestRegs > 0) {
             ss << ", ";
         }
-        printReg(ss, _srcRegIdx[0]);
+        printReg(ss, srcRegIdx(0));
     }
 
     // Print the shift, mask begin and mask end
diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
index 8566f04bb..596d78d25 100644
--- a/src/arch/power/insts/mem.cc
+++ b/src/arch/power/insts/mem.cc
@@ -53,13 +53,13 @@ MemDispOp::generateDisassembly(
             // If the instruction updates the source register with the
             // EA, then this source register is placed in position 0,
             // therefore we print the last destination register.
-            printReg(ss, _destRegIdx[_numDestRegs-1]);
+            printReg(ss, destRegIdx(_numDestRegs-1));
         }
     }
 
     // Print the data register for a store
     else {
-        printReg(ss, _srcRegIdx[1]);
+        printReg(ss, srcRegIdx(1));
     }
 
     // Print the displacement
@@ -67,7 +67,7 @@ MemDispOp::generateDisassembly(
 
     // Print the address register
     ss << "(";
-    printReg(ss, _srcRegIdx[0]);
+    printReg(ss, srcRegIdx(0));
     ss << ")";
 
     return ss.str();
diff --git a/src/arch/power/insts/misc.cc b/src/arch/power/insts/misc.cc
index 5d12eb5d0..25177c573 100644
--- a/src/arch/power/insts/misc.cc
+++ b/src/arch/power/insts/misc.cc
@@ -39,7 +39,7 @@ MiscOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
     // Print the first destination only
     if (_numDestRegs > 0) {
-        printReg(ss, _destRegIdx[0]);
+        printReg(ss, destRegIdx(0));
     }
 
     // Print the (possibly) two source registers
@@ -47,10 +47,10 @@ MiscOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
         if (_numDestRegs > 0) {
             ss << ", ";
         }
-        printReg(ss, _srcRegIdx[0]);
+        printReg(ss, srcRegIdx(0));
         if (_numSrcRegs > 1) {
           ss << ", ";
-          printReg(ss, _srcRegIdx[1]);
+          printReg(ss, srcRegIdx(1));
         }
     }
 
diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
index cf4b221b5..0b54bb05d 100644
--- a/src/arch/riscv/insts/amo.cc
+++ b/src/arch/riscv/insts/amo.cc
@@ -81,8 +81,8 @@ LoadReservedMicro::generateDisassembly(
         Addr pc, const Loader::SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
-            << registerName(_srcRegIdx[0]) << ')';
+    ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ("
+            << registerName(srcRegIdx(0)) << ')';
     return ss.str();
 }
 
@@ -110,9 +110,9 @@ StoreCondMicro::generateDisassembly(
         Addr pc, const Loader::SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
-            << registerName(_srcRegIdx[1]) << ", ("
-            << registerName(_srcRegIdx[0]) << ')';
+    ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
+            << registerName(srcRegIdx(1)) << ", ("
+            << registerName(srcRegIdx(0)) << ')';
     return ss.str();
 }
 
@@ -140,9 +140,9 @@ AtomicMemOpMicro::generateDisassembly(
         Addr pc, const Loader::SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
-            << registerName(_srcRegIdx[1]) << ", ("
-            << registerName(_srcRegIdx[0]) << ')';
+    ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
+            << registerName(srcRegIdx(1)) << ", ("
+            << registerName(srcRegIdx(0)) << ')';
     return ss.str();
 }
 
diff --git a/src/arch/riscv/insts/compressed.cc b/src/arch/riscv/insts/compressed.cc
index 65ccdf219..327bcf462 100644
--- a/src/arch/riscv/insts/compressed.cc
+++ b/src/arch/riscv/insts/compressed.cc
@@ -43,8 +43,8 @@ CompRegOp::generateDisassembly(
         Addr pc, const Loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-        registerName(_srcRegIdx[0]);
+    ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+        registerName(srcRegIdx(0));
     return ss.str();
 }
 
diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc
index d1dae7629..dde330a68 100644
--- a/src/arch/riscv/insts/mem.cc
+++ b/src/arch/riscv/insts/mem.cc
@@ -46,8 +46,8 @@ string
 Load::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-        offset << '(' << registerName(_srcRegIdx[0]) << ')';
+    ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+        offset << '(' << registerName(srcRegIdx(0)) << ')';
     return ss.str();
 }
 
@@ -55,8 +55,8 @@ string
 Store::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
-        offset << '(' << registerName(_srcRegIdx[0]) << ')';
+    ss << mnemonic << ' ' << registerName(srcRegIdx(1)) << ", " <<
+        offset << '(' << registerName(srcRegIdx(0)) << ')';
     return ss.str();
 }
 
diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc
index 35f9ccd4b..c04dae63e 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -46,12 +46,12 @@ string
 RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-        registerName(_srcRegIdx[0]);
+    ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+        registerName(srcRegIdx(0));
     if (_numSrcRegs >= 2)
-        ss << ", " << registerName(_srcRegIdx[1]);
+        ss << ", " << registerName(srcRegIdx(1));
     if (_numSrcRegs >= 3)
-        ss << ", " << registerName(_srcRegIdx[2]);
+        ss << ", " << registerName(srcRegIdx(2));
     return ss.str();
 }
 
@@ -59,14 +59,14 @@ string
 CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
+    ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ";
     auto data = CSRData.find(csr);
     if (data != CSRData.end())
         ss << data->second.name;
     else
         ss << "?? (" << hex << "0x" << csr << dec << ")";
     if (_numSrcRegs > 0)
-        ss << ", " << registerName(_srcRegIdx[0]);
+        ss << ", " << registerName(srcRegIdx(0));
     else
         ss << uimm;
     return ss.str();
@@ -77,8 +77,8 @@ SystemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
     if (strcmp(mnemonic, "fence_vma") == 0) {
         stringstream ss;
-        ss << mnemonic << ' ' << registerName(_srcRegIdx[0]) << ", " <<
-            registerName(_srcRegIdx[1]);
+        ss << mnemonic << ' ' << registerName(srcRegIdx(0)) << ", " <<
+            registerName(srcRegIdx(1));
         return ss.str();
     }
 
diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa
index 9376d140d..b9709126f 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -36,7 +36,7 @@ def format CROp(code, *opt_flags) {{
 }};
 
 def format CIAddi4spnOp(imm_code, code, imm_type='int64_t', *opt_flags) {{
-    regs = ['_destRegIdx[0]', '_srcRegIdx[0]']
+    regs = ['destRegIdx(0)', 'srcRegIdx(0)']
     iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
@@ -49,7 +49,7 @@ def format CIAddi4spnOp(imm_code, code, imm_type='int64_t', *opt_flags) {{
 def format CIOp(imm_code, code, imm_type='int64_t', *opt_flags) {{
     iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
         {'code': code, 'imm_code': imm_code,
-         'regs': '_destRegIdx[0]'}, opt_flags)
+         'regs': 'destRegIdx(0)'}, opt_flags)
     header_output = ImmDeclare.subst(iop)
     decoder_output = ImmConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
@@ -89,10 +89,10 @@ def format CBOp(code, *opt_flags) {{
                 if (CIMM3<2:2> > 0)
                     imm |= ~((int64_t)0xFF);
                """
-    regs = '_srcRegIdx[0]'
+    regs = 'srcRegIdx(0)'
     iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': imm_code,
-         'regs': '_srcRegIdx[0]'}, opt_flags)
+         'regs': 'srcRegIdx(0)'}, opt_flags)
     header_output = BranchDeclare.subst(iop)
     decoder_output = ImmConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
@@ -162,7 +162,7 @@ def template CBasicExecute {{
 }};
 
 def format CompressedROp(code, *opt_flags) {{
-    regs = ['_destRegIdx[0]','_srcRegIdx[1]']
+    regs = ['destRegIdx(0)','srcRegIdx(1)']
     iop = InstObjParams(name, Name, 'RegOp',
         {'code': code, 'regs': ','.join(regs)}, opt_flags)
     header_output = CBasicDeclare.subst(iop)
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 5c756951b..04a469f83 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -275,7 +275,7 @@ def template JumpExecute {{
     %(class_name)s::branchTarget(ThreadContext *tc) const
     {
         PCState pc = tc->pcState();
-        pc.set((tc->readIntReg(_srcRegIdx[0].index()) + imm)&~0x1);
+        pc.set((tc->readIntReg(srcRegIdx(0).index()) + imm)&~0x1);
         return pc;
     }
 
@@ -286,10 +286,10 @@ def template JumpExecute {{
         std::stringstream ss;
         ss << mnemonic << ' ';
         if (QUADRANT == 0x3)
-            ss << registerName(_destRegIdx[0]) << ", "
-               << imm << "(" << registerName(_srcRegIdx[0]) << ")";
+            ss << registerName(destRegIdx(0)) << ", "
+               << imm << "(" << registerName(srcRegIdx(0)) << ")";
         else
-            ss << registerName(_srcRegIdx[0]);
+            ss << registerName(srcRegIdx(0));
         return ss.str();
     }
 }};
@@ -409,7 +409,7 @@ def format ROp(code, *opt_flags) {{
 
 def format IOp(code, imm_type='int64_t', imm_code='imm = sext<12>(IMM12);',
               *opt_flags) {{
-    regs = ['_destRegIdx[0]','_srcRegIdx[0]']
+    regs = ['destRegIdx(0)','srcRegIdx(0)']
     iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
         {'imm_code': imm_code, 'code': code,
          'regs': ','.join(regs)}, opt_flags)
@@ -420,7 +420,7 @@ def format IOp(code, imm_type='int64_t', imm_code='imm = sext<12>(IMM12);',
 }};
 
 def format FenceOp(code, imm_type='int64_t', *opt_flags) {{
-    regs = ['_destRegIdx[0]','_srcRegIdx[0]']
+    regs = ['destRegIdx(0)','srcRegIdx(0)']
     iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
         {'code': code, 'imm_code': 'imm = sext<12>(IMM12);',
          'regs': ','.join(regs)}, opt_flags)
@@ -438,7 +438,7 @@ def format BOp(code, *opt_flags) {{
                       IMMSIGN << 12;
                 imm = sext<13>(imm);
                """
-    regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
+    regs = ['srcRegIdx(0)','srcRegIdx(1)']
     iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
@@ -449,7 +449,7 @@ def format BOp(code, *opt_flags) {{
 }};
 
 def format Jump(code, *opt_flags) {{
-    regs = ['_srcRegIdx[0]']
+    regs = ['srcRegIdx(0)']
     iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': 'imm = sext<12>(IMM12);',
          'regs': ','.join(regs)}, opt_flags)
@@ -460,7 +460,7 @@ def format Jump(code, *opt_flags) {{
 }};
 
 def format UOp(code, *opt_flags) {{
-    regs = ['_destRegIdx[0]']
+    regs = ['destRegIdx(0)']
     iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': 'imm = IMM20;',
          'regs': ','.join(regs)}, opt_flags)
@@ -479,7 +479,7 @@ def format JOp(code, *opt_flags) {{
                 imm = sext<21>(imm);
                """
     pc = 'pc.set(pc.pc() + imm);'
-    regs = ['_destRegIdx[0]']
+    regs = ['destRegIdx(0)']
     iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
diff --git a/src/arch/sparc/insts/blockmem.cc b/src/arch/sparc/insts/blockmem.cc
index 6b6f2b0f2..d83332b12 100644
--- a/src/arch/sparc/insts/blockmem.cc
+++ b/src/arch/sparc/insts/blockmem.cc
@@ -41,17 +41,17 @@ BlockMemMicro::generateDisassembly(
 
     printMnemonic(response, mnemonic);
     if (save) {
-        printReg(response, _srcRegIdx[0]);
+        printReg(response, srcRegIdx(0));
         ccprintf(response, ", ");
     }
     ccprintf(response, "[ ");
-    printReg(response, _srcRegIdx[!save ? 0 : 1]);
+    printReg(response, srcRegIdx(!save ? 0 : 1));
     ccprintf(response, " + ");
-    printReg(response, _srcRegIdx[!save ? 1 : 2]);
+    printReg(response, srcRegIdx(!save ? 1 : 2));
     ccprintf(response, " ]");
     if (load) {
         ccprintf(response, ", ");
-        printReg(response, _destRegIdx[0]);
+        printReg(response, destRegIdx(0));
     }
 
     return response.str();
@@ -67,18 +67,18 @@ BlockMemImmMicro::generateDisassembly(
 
     printMnemonic(response, mnemonic);
     if (save) {
-        printReg(response, _srcRegIdx[1]);
+        printReg(response, srcRegIdx(1));
         ccprintf(response, ", ");
     }
     ccprintf(response, "[ ");
-    printReg(response, _srcRegIdx[0]);
+    printReg(response, srcRegIdx(0));
     if (imm >= 0)
         ccprintf(response, " + 0x%x ]", imm);
     else
         ccprintf(response, " + -0x%x ]", -imm);
     if (load) {
         ccprintf(response, ", ");
-        printReg(response, _destRegIdx[0]);
+        printReg(response, destRegIdx(0));
     }
 
     return response.str();
diff --git a/src/arch/sparc/insts/branch.cc b/src/arch/sparc/insts/branch.cc
index 52517e620..2f195550e 100644
--- a/src/arch/sparc/insts/branch.cc
+++ b/src/arch/sparc/insts/branch.cc
@@ -46,7 +46,7 @@ Branch::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
     std::stringstream response;
 
     printMnemonic(response, mnemonic);
-    printRegArray(response, _srcRegIdx, _numSrcRegs);
+    printRegArray(response, &srcRegIdx(0), _numSrcRegs);
     if (_numDestRegs && _numSrcRegs)
             response << ", ";
     printDestReg(response, 0);
@@ -61,7 +61,7 @@ BranchImm13::generateDisassembly(
     std::stringstream response;
 
     printMnemonic(response, mnemonic);
-    printRegArray(response, _srcRegIdx, _numSrcRegs);
+    printRegArray(response, &srcRegIdx(0), _numSrcRegs);
     if (_numSrcRegs > 0)
         response << ", ";
     ccprintf(response, "0x%x", imm);
diff --git a/src/arch/sparc/insts/integer.cc b/src/arch/sparc/insts/integer.cc
index b92afe234..d58334f46 100644
--- a/src/arch/sparc/insts/integer.cc
+++ b/src/arch/sparc/insts/integer.cc
@@ -40,7 +40,7 @@ bool
 IntOp::printPseudoOps(std::ostream &os, Addr pc,
                       const Loader::SymbolTable *symbab) const
 {
-    if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].index() == 0) {
+    if (!std::strcmp(mnemonic, "or") && srcRegIdx(0).index() == 0) {
         printMnemonic(os, "mov");
         printSrcReg(os, 1);
         ccprintf(os, ", ");
@@ -55,7 +55,7 @@ IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
                          const Loader::SymbolTable *symbab) const
 {
     if (!std::strcmp(mnemonic, "or")) {
-        if (_numSrcRegs > 0 && _srcRegIdx[0].index() == 0) {
+        if (_numSrcRegs > 0 && srcRegIdx(0).index() == 0) {
             if (imm == 0) {
                 printMnemonic(os, "clr");
             } else {
@@ -83,7 +83,7 @@ IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
     if (printPseudoOps(response, pc, symtab))
         return response.str();
     printMnemonic(response, mnemonic);
-    printRegArray(response, _srcRegIdx, _numSrcRegs);
+    printRegArray(response, &srcRegIdx(0), _numSrcRegs);
     if (_numDestRegs && _numSrcRegs)
         response << ", ";
     printDestReg(response, 0);
@@ -98,7 +98,7 @@ IntOpImm::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
     if (printPseudoOps(response, pc, symtab))
         return response.str();
     printMnemonic(response, mnemonic);
-    printRegArray(response, _srcRegIdx, _numSrcRegs);
+    printRegArray(response, &srcRegIdx(0), _numSrcRegs);
     if (_numSrcRegs > 0)
         response << ", ";
     ccprintf(response, "%#x", imm);
diff --git a/src/arch/sparc/insts/mem.cc b/src/arch/sparc/insts/mem.cc
index 594f08ba3..2d7ebc62f 100644
--- a/src/arch/sparc/insts/mem.cc
+++ b/src/arch/sparc/insts/mem.cc
@@ -40,11 +40,11 @@ Mem::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
     printMnemonic(response, mnemonic);
     if (store) {
-        printReg(response, _srcRegIdx[0]);
+        printReg(response, srcRegIdx(0));
         ccprintf(response, ", ");
     }
     ccprintf(response, "[");
-    if (_srcRegIdx[!store ? 0 : 1].index() != 0) {
+    if (srcRegIdx(!store ? 0 : 1).index() != 0) {
         printSrcReg(response, !store ? 0 : 1);
         ccprintf(response, " + ");
     }
@@ -52,7 +52,7 @@ Mem::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
     ccprintf(response, "]");
     if (load) {
         ccprintf(response, ", ");
-        printReg(response, _destRegIdx[0]);
+        printReg(response, destRegIdx(0));
     }
 
     return response.str();
@@ -67,12 +67,12 @@ MemImm::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
     printMnemonic(response, mnemonic);
     if (save) {
-        printReg(response, _srcRegIdx[0]);
+        printReg(response, srcRegIdx(0));
         ccprintf(response, ", ");
     }
     ccprintf(response, "[");
-    if (_srcRegIdx[!save ? 0 : 1].index() != 0) {
-        printReg(response, _srcRegIdx[!save ? 0 : 1]);
+    if (srcRegIdx(!save ? 0 : 1).index() != 0) {
+        printReg(response, srcRegIdx(!save ? 0 : 1));
         ccprintf(response, " + ");
     }
     if (imm >= 0)
@@ -81,7 +81,7 @@ MemImm::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
         ccprintf(response, "-%#x]", -imm);
     if (load) {
         ccprintf(response, ", ");
-        printReg(response, _destRegIdx[0]);
+        printReg(response, destRegIdx(0));
     }
 
     return response.str();
diff --git a/src/arch/sparc/insts/priv.cc b/src/arch/sparc/insts/priv.cc
index 65113548f..f17853f9a 100644
--- a/src/arch/sparc/insts/priv.cc
+++ b/src/arch/sparc/insts/priv.cc
@@ -65,7 +65,7 @@ WrPriv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
     ccprintf(response, " ");
     // If the first reg is %g0, don't print it.
     // This improves readability
-    if (_srcRegIdx[0].index() != 0) {
+    if (srcRegIdx(0).index() != 0) {
         printSrcReg(response, 0);
         ccprintf(response, ", ");
     }
@@ -86,7 +86,7 @@ WrPrivImm::generateDisassembly(
     ccprintf(response, " ");
     // If the first reg is %g0, don't print it.
     // This improves readability
-    if (_srcRegIdx[0].index() != 0) {
+    if (srcRegIdx(0).index() != 0) {
         printSrcReg(response, 0);
         ccprintf(response, ", ");
     }
diff --git a/src/arch/sparc/insts/static_inst.cc b/src/arch/sparc/insts/static_inst.cc
index 9e7bc6747..467b38fd3 100644
--- a/src/arch/sparc/insts/static_inst.cc
+++ b/src/arch/sparc/insts/static_inst.cc
@@ -59,7 +59,7 @@ SparcStaticInst::printMnemonic(std::ostream &os, const char *mnemonic)
 }
 
 void
-SparcStaticInst::printRegArray(std::ostream &os, const RegId indexArray[],
+SparcStaticInst::printRegArray(std::ostream &os, const RegId *indexArray,
                                int num) const
 {
     if (num <= 0)
@@ -81,14 +81,14 @@ void
 SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
 {
     if (_numSrcRegs > reg)
-        printReg(os, _srcRegIdx[reg]);
+        printReg(os, srcRegIdx(reg));
 }
 
 void
 SparcStaticInst::printDestReg(std::ostream &os, int reg) const
 {
     if (_numDestRegs > reg)
-        printReg(os, _destRegIdx[reg]);
+        printReg(os, destRegIdx(reg));
 }
 
 void
@@ -257,10 +257,10 @@ SparcStaticInst::generateDisassembly(
     // a third one, it's a read-modify-write dest (Rc),
     // e.g. for CMOVxx
     if (_numSrcRegs > 0)
-        printReg(ss, _srcRegIdx[0]);
+        printReg(ss, srcRegIdx(0));
     if (_numSrcRegs > 1) {
         ss << ",";
-        printReg(ss, _srcRegIdx[1]);
+        printReg(ss, srcRegIdx(1));
     }
 
     // just print the first dest... if there's a second one,
@@ -268,7 +268,7 @@ SparcStaticInst::generateDisassembly(
     if (_numDestRegs > 0) {
         if (_numSrcRegs > 0)
             ss << ",";
-        printReg(ss, _destRegIdx[0]);
+        printReg(ss, destRegIdx(0));
     }
 
     return ss.str();
diff --git a/src/arch/sparc/insts/static_inst.hh b/src/arch/sparc/insts/static_inst.hh
index fcfb522cf..0237c986e 100644
--- a/src/arch/sparc/insts/static_inst.hh
+++ b/src/arch/sparc/insts/static_inst.hh
@@ -99,7 +99,7 @@ class SparcStaticInst : public StaticInst
     void printDestReg(std::ostream &os, int reg) const;
 
     void printRegArray(std::ostream &os,
-        const RegId indexArray[], int num) const;
+        const RegId *indexArray, int num) const;
 
     void advancePC(PCState &pcState) const override;
 
diff --git a/src/arch/sparc/insts/trap.cc b/src/arch/sparc/insts/trap.cc
index 693ec8802..120900ac0 100644
--- a/src/arch/sparc/insts/trap.cc
+++ b/src/arch/sparc/insts/trap.cc
@@ -38,10 +38,10 @@ Trap::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
     printMnemonic(response, mnemonic);
     ccprintf(response, " ");
-    printReg(response, _srcRegIdx[0]);
+    printReg(response, srcRegIdx(0));
     ccprintf(response, ", 0x%x", trapNum);
     ccprintf(response, ", or ");
-    printReg(response, _srcRegIdx[1]);
+    printReg(response, srcRegIdx(1));
     return response.str();
 }
 
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index f8e137b5c..387ed903d 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -107,14 +107,14 @@ namespace X86ISA
     X86StaticInst::printSrcReg(std::ostream &os, int reg, int size) const
     {
         if (_numSrcRegs > reg)
-            printReg(os, _srcRegIdx[reg], size);
+            printReg(os, srcRegIdx(reg), size);
     }
 
     void
     X86StaticInst::printDestReg(std::ostream &os, int reg, int size) const
     {
         if (_numDestRegs > reg)
-            printReg(os, _destRegIdx[reg], size);
+            printReg(os, destRegIdx(reg), size);
     }
 
     void
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh
index bdf82d899..de41f472f 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -105,7 +105,7 @@ namespace X86ISA
         inline uint64_t merge(uint64_t into, uint64_t val, int size) const
         {
             X86IntReg reg = into;
-            if (_destRegIdx[0].index() & IntFoldBit)
+            if (destRegIdx(0).index() & IntFoldBit)
             {
                 reg.H = val;
                 return reg;
@@ -136,7 +136,7 @@ namespace X86ISA
         {
             X86IntReg reg = from;
             DPRINTF(X86, "Picking with size %d\n", size);
-            if (_srcRegIdx[idx].index() & IntFoldBit)
+            if (srcRegIdx(idx).index() & IntFoldBit)
                 return reg.H;
             switch(size)
             {
@@ -157,7 +157,7 @@ namespace X86ISA
         {
             X86IntReg reg = from;
             DPRINTF(X86, "Picking with size %d\n", size);
-            if (_srcRegIdx[idx].index() & IntFoldBit)
+            if (srcRegIdx(idx).index() & IntFoldBit)
                 return reg.SH;
             switch(size)
             {
diff --git a/src/arch/x86/isa/formats/cpuid.isa b/src/arch/x86/isa/formats/cpuid.isa
index 41e2ac205..0a9a015c2 100644
--- a/src/arch/x86/isa/formats/cpuid.isa
+++ b/src/arch/x86/isa/formats/cpuid.isa
@@ -61,7 +61,7 @@ output decoder {{
 
         printMnemonic(response, mnemonic);
         ccprintf(response, " ");
-        printReg(response, _srcRegIdx[0], machInst.opSize);
+        printReg(response, srcRegIdx(0), machInst.opSize);
         return response.str();
     }
 }};
diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa
index b5fe34c51..99fc85b83 100644
--- a/src/arch/x86/isa/formats/monitor_mwait.isa
+++ b/src/arch/x86/isa/formats/monitor_mwait.isa
@@ -28,7 +28,7 @@ output decoder {{
 
         printMnemonic(response, mnemonic);
         ccprintf(response, " ");
-        printReg(response, _srcRegIdx[0], machInst.opSize);
+        printReg(response, srcRegIdx(0), machInst.opSize);
         return response.str();
     }
 }};
@@ -105,7 +105,7 @@ output decoder {{
     {
         std::stringstream response;
 
-        // Although mwait could take hints from eax and ecx, the _srcRegIdx
+        // Although mwait could take hints from eax and ecx, the srcRegIdx
         // is not set, and thus should not be printed here
         printMnemonic(response, mnemonic);
         return response.str();
diff --git a/src/arch/x86/isa/formats/syscall.isa b/src/arch/x86/isa/formats/syscall.isa
index d4402d8bb..3044d3a1b 100644
--- a/src/arch/x86/isa/formats/syscall.isa
+++ b/src/arch/x86/isa/formats/syscall.isa
@@ -67,7 +67,7 @@ output decoder {{
 
         printMnemonic(response, mnemonic);
         ccprintf(response, " ");
-        printReg(response, _srcRegIdx[0], machInst.opSize);
+        printReg(response, srcRegIdx(0), machInst.opSize);
         return response.str();
     }
 }};
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 65561706d..4f3dd04fe 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -93,6 +93,12 @@ class StaticInst : public RefCounted, public StaticInstFlags
         MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
     };
 
+  private:
+    /// See destRegIdx().
+    RegId _destRegIdx[MaxInstDestRegs];
+    /// See srcRegIdx().
+    RegId _srcRegIdx[MaxInstSrcRegs];
+
   protected:
 
     /// Flag values for this instruction.
@@ -232,10 +238,14 @@ class StaticInst : public RefCounted, public StaticInstFlags
     /// Only the entries from 0 through numDestRegs()-1 are valid.
     const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
 
+    void setDestRegIdx(int i, const RegId &val) { _destRegIdx[i] = val; }
+
     /// Return logical index (architectural reg num) of i'th source reg.
     /// Only the entries from 0 through numSrcRegs()-1 are valid.
     const RegId& srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 
+    void setSrcRegIdx(int i, const RegId &val) { _srcRegIdx[i] = val; }
+
     /// Pointer to a statically allocated "null" instruction object.
     static StaticInstPtr nullStaticInstPtr;
 
@@ -247,11 +257,6 @@ class StaticInst : public RefCounted, public StaticInstFlags
 
   protected:
 
-    /// See destRegIdx().
-    RegId _destRegIdx[MaxInstDestRegs];
-    /// See srcRegIdx().
-    RegId _srcRegIdx[MaxInstSrcRegs];
-
     /**
      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
      * methods.  Also useful to readily identify instructions from