From: lkcl <lkcl@web>
Date: Sun, 10 Apr 2022 15:39:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2806
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2cfd4988a442f2d04294a58938f39e6088489090;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 3067efe4f..b8a9843f5 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -56,7 +56,9 @@ Parallel Carry Lookahead.
 It can clearly be seen that the carry chains from one
 64 bit add to the next, the end result being that a
 256-bit "Big Integer Add" has been performed, and that
-CA contains the 257th bit.
+CA contains the 257th bit.  A one-instruction 512-bit Add
+may be performed by setting VL=8, and a one-instruction
+1024-bit add by setting VL=16, and so on.
 
 # v3.0B/v3.1 relevant instructions